Exam 2: Embedded Systems and Communication Protocols
Exam 1: Chip Design, Protocols, and Communication24 Questions
Exam 2: Embedded Systems and Communication Protocols25 Questions
Exam 3: Computer Bus and IO Operations22 Questions
Exam 4: ISA, Communication Modes, Wlan, Serial Protocols, ARM Processors, and Real-Time Systems25 Questions
Exam 5: Real Time Operating Systems and Scheduling Techniques25 Questions
Exam 6: Real-Time Operating System Scheduling and Job Management14 Questions
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The AT bus is also known as the ____ bus.
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C
Which of following is not a valid bus in computer system ?
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B
Which common bus specification provides the fastest data transfer rate?
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C
Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system's environment by computing specific results for real-time applications without any kind of postponement ?
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process that is based on IPC mechanism which executes on different systems and can communicate with other processes using message based communication, is called ________
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The step where in the results stored in the temporary register is transferred into the permanent register is called as ______
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Which of the following has a quadruple buffered receiver and a double buffered transmitter?
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______ is a technology that allows telephone calls to be made over computer networks like the Internet.
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Which scheme/ strategy is suitable to establish the communication between the access point (AP) and the infrastructure of LANs?
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Suppose a TCP connection is transferring a file of 1000 bytes. The first byte is numbered 10001. What is the sequence number of the segment if all data is sent in only one segment?
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Which development tool can facilitate the creation and modification of source programs in addition to assembly and higher -level languages?
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Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system?
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Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus?
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Bytes of data being transferred in each connection are numbered by TCP. These numbers start with a _________
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If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______
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For applications that demand very high data-processing requirements, or if double precision floating point calculation is needed, then best choice will be
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While designing an embedded system, which sub-task oriented process allocates the time steps for various modules that share the similar resources?
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What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications?
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