Question 1

The operation that does not involves clock cycles is___________

Accepted Answer

A) installation of a device 
B) execute 
C) fetch 
D) decode 
A) installation of a device 
B) execute 
C) fetch 
D) decode A

Question 2

The portion of the processor which contains the hardware required to fetch the operations is___________

Accepted Answer

A) datapath 
B) processor 
C) control 
D) output unit 
A) datapath 
B) processor 
C) control 
D) output unit A

Question 3

The number of sign bits in a 32-bit IEEE format is

Accepted Answer

A) 1 
B) 11 
C) 9 
D) 23 
A) 1 
B) 11 
C) 9 
D) 23 A

Question 4

What does PC stand for?

Accepted Answer

A) program changer 
B) program counter 
C) performance counter 
D) performance changer 
A) program changer 
B) program counter 
C) performance counter 
D) performance changer

Question 5

Causing the CPU to step through a series of micro operations is called___________

Accepted Answer

A) execution 
B) runtime 
C) sequencing 
D) pipelining 
A) execution 
B) runtime 
C) sequencing 
D) pipelining

Question 6

Which of the following holds the last instruction fetched?

Accepted Answer

A) pc 
B) mar 
C) mbr 
D) ir 
A) pc 
B) mar 
C) mbr 
D) ir

Question 7

CISC stands for___________

Accepted Answer

A) complex information sensed cpu 
B) complex instruction set computer 
C) complex intelligence sensed cpu 
D) complex instruction set cpu 
A) complex information sensed cpu 
B) complex instruction set computer 
C) complex intelligence sensed cpu 
D) complex instruction set cpu

Question 8

In___________mapping, the data can be mapped anywhere in the Cache Memory.

Accepted Answer

A) associative 
B) direct 
C) set associative 
D) indirect 
A) associative 
B) direct 
C) set associative 
D) indirect

Question 9

What does MBR stand for?

Accepted Answer

A) main buffer register 
B) memory buffer routine 
C) main buffer routine 
D) memory buffer register 
A) main buffer register 
B) memory buffer routine 
C) main buffer routine 
D) memory buffer register

Question 10

Which of the following processor has a fixed length of instructions?

Accepted Answer

A) cisc 
B) risc 
C) epic 
D) multi-core 
A) cisc 
B) risc 
C) epic 
D) multi-core

Question 11

Cache Memory is implemented using the DRAM chips.

Accepted Answer

A) True 
 B)False

Question 12

The number of clock cycles per second is referred as___________

Accepted Answer

A) clock speed 
B) clock frequency 
C) clock rate 
D) clock timing 
A) clock speed 
B) clock frequency 
C) clock rate 
D) clock timing

Question 13

The functions of execution and sequencing are performed by using___________

Accepted Answer

A) input signals 
B) output signals 
C) control signals 
D) cpu 
A) input signals 
B) output signals 
C) control signals 
D) cpu

Question 14

The transfer between CPU and Cache is

Accepted Answer

A) block transfer 
B) word transfer 
C) set transfer 
D) associative transfer 
A) block transfer 
B) word transfer 
C) set transfer 
D) associative transfer

Question 15

Whenever the data is found in the cache memory it is called as___________

Accepted Answer

A) hit 
B) miss 
C) found 
D) error 
A) hit 
B) miss 
C) found 
D) error

Question 16

LRU stands for___________

Accepted Answer

A) low rate usage 
B) least rate usage 
C) least recently used 
D) low required usage 
A) low rate usage 
B) least rate usage 
C) least recently used 
D) low required usage

Question 17

It takes one clock cycle to perform a basic operation.

Accepted Answer

A) True 
 B)False

Question 18

What is the high speed memory between the main memory and the CPU called?

Accepted Answer

A) register memory 
B) cache memory 
C) storage memory 
D) virtual memory 
A) register memory 
B) cache memory 
C) storage memory 
D) virtual memory

Question 19

Control Unit acts as the central nervous system of the computer.

Accepted Answer

A) True 
 B)False

Question 20

Which of the following is not a write policy to avoid Cache Coherence?

Accepted Answer

A) write through 
B) write within 
C) write back 
D) buffered write 
A) write through 
B) write within 
C) write back 
D) buffered write

Exam 5: Processor and Memory Fundamentals

The operation that does not involves clock cycles is___________

The portion of the processor which contains the hardware required to fetch the operations is___________

The number of sign bits in a 32-bit IEEE format is

What does PC stand for?

Causing the CPU to step through a series of micro operations is called___________

Which of the following holds the last instruction fetched?

CISC stands for___________

In___________mapping, the data can be mapped anywhere in the Cache Memory.

What does MBR stand for?

Which of the following processor has a fixed length of instructions?

Cache Memory is implemented using the DRAM chips.

The number of clock cycles per second is referred as___________

The functions of execution and sequencing are performed by using___________

The transfer between CPU and Cache is

Whenever the data is found in the cache memory it is called as___________

LRU stands for___________

It takes one clock cycle to perform a basic operation.

What is the high speed memory between the main memory and the CPU called?

Control Unit acts as the central nervous system of the computer.

Which of the following is not a write policy to avoid Cache Coherence?

Operating System

Operating System and Software

Operating System and Computer Basics: Formatting, Clipboard, Radio Buttons, Bankers Algorithm, and More

Computer Software and Operating System

Computer Architecture and Memory

Computer Science and Information Technology on Raid, Middleware, and CPU Scheduling

Understanding Process Scheduling in Operating Systems

Operating System and Process Management

Process Scheduling and Synchronization in Multi-Programming Environment

Process Management and Interprocess Communication in Unix

Semaphores, Spinlocks, and Monitors: Understanding Synchronization in Operating Systems

Concurrency Control and Deadlock Prevention in Operating Systems

Deadlock and Resource Allocation in Computer Systems

Memory Management and Swapping Techniques

Memory Management in Operating Systems

Understanding Paging and Memory Management in Operating Systems

Understanding Virtual Memory and Page Replacement Algorithms

Virtual Memory, Segmentation, and Disk Management

Disk Management and I/O Subsystem

Linux Kernel and System Structures

Thread Management and Synchronization in Operating Systems

Operating System Concepts: System Calls, Threads, and Signals

Operating System and Thread Pool

Operating System and Memory Management

Process Control and Memory Management

Linux Kernel, File Systems, Bootloaders and Distributions

Filters