The Carry Propagation Delay in Full- Adder Circuits

Multiple Choice

The carry propagation delay in full- adder circuits:

A) decreases in a direct ratio to the total number of FA stages.
B) is cumulative for each stage and limits the speed at which arithmetic operations are performed.
C) increases in a direct ratio to the total number of FA stages but are not a factor in limiting the speed of arithmetic operations.
D) is normally not a consideration because the delays are usually in the nanosecond range.