Multiple Choice
-Refer to Figure 8- 5. What occurs at point 'V' on the timing diagram?
A) The outputs are cleared - set to LOW.
B) Data is loaded into the register from the parallel inputs.
C) The serial inputs are loaded into the register.
D) The parallel inputs are inhibited - prevented from loading into the register.
Correct Answer:

Verified
Correct Answer:
Verified
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