First-Level Cache in a XEON CPU That Stores Decoded Instructions

Multiple Choice

first-level cache in a XEON CPU that stores decoded instructions
and delivers them to the processor at high speed.

A) CISC
B) external clock speed
C) data bus
D) address bus
E) core
F) hyper-threading
G) control bus
H) instruction set
I) RISC
J) execution-based cache