Exam 6: System Integration and Performance

A portion of the CPU, separate from the components that fetch and execute instructions, monitors the bus continuously for interrupt signals and copies them to a(n) ____________________.

____ is an approach that partitions processing and other tasks among multiple computer systems.

A special-purpose register called the ____________________ always points to the next empty address in the stack and is incremented or decremented automatically each time the stack is pushed or popped.

One task performed by a storage device controller is translating logical write operations into ____ write operations.

The ____ governs the format, content, and timing of data, memory addresses, and control messages sent across the bus.

A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors.

​Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.

A ____ connects secondary storage devices to the system bus.

A(n) ____________________ is a small reserved area of main memory (usually DRAM or SRAM) that holds data in transit from one device to another and is required to resolve differences in data transfer unit size.

A ____ is a mathematical compression technique implemented as a program.

Most performance benefits of a cache occur during ____.

As buffer size increases above ____ bytes, CPU cycle consumption decreases at a linear rate.

Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes.

Explain why overall system performance is reduced in traditional computer architecture, using a bus master.

In the simplest sense, a(n) ____________________ is just a set of communication lines.

MP3 compresses the audio data stream by discarding information about masked sounds or representing them with fewer bits.

The ratio of cache hits to read accesses is called the cache's ____.

Secondary storage devices are much faster than the system bus.

Mismatches in data transfer rate and data transfer unit size are addressed in part by ____________________, which consumes substantial CPU resources.

Many computer system designers rely on ____ to implement disk caching.