Question 1

Triple angle brackets mark in a statement inside main function, what does it indicates?

Accepted Answer

A) a call from host code to device code 
B) a call from device code to host code 
C) less than comparison 
D) greater than comparison 
A) a call from host code to device code 
B) a call from device code to host code 
C) less than comparison 
D) greater than comparison A

Question 2

What is the equivalent of general C program with CUDA C:
Int main(void)
{
Printf("Hello, World!
");
Return 0;
}

Accepted Answer

A)  int main ( void )
{
Kernel >>();
Printf("hello, world!\n");
Return 0;
} 
B) __global__ void kernel( void ) { }
Int main ( void ) { kernel >>();
Printf("hello, world!\n");
Return 0;
} 
C) __global__ void kernel( void ) {
Kernel >>();
Printf("hello, world!\n");
Return 0;
} 
D) __global__ int main ( void ) {
Kernel >>();
Printf("hello, world!\n");
Return 0;
} 
A)  int main ( void )
{
Kernel >>();
Printf("hello, world!\n");
Return 0;
} 
B) __global__ void kernel( void ) { }
Int main ( void ) { kernel >>();
Printf("hello, world!\n");
Return 0;
} 
C) __global__ void kernel( void ) {
Kernel >>();
Printf("hello, world!\n");
Return 0;
} 
D) __global__ int main ( void ) {
Kernel >>();
Printf("hello, world!\n");
Return 0;
} B

Question 3

NVIDIA CUDA Warp is made up of how many threads?

Accepted Answer

A) 512 
B) 1024 
C) 312 
D) 32 
A) 512 
B) 1024 
C) 312 
D) 32 D

Question 4

The CUDA architecture consists of --------- for parallel computing kernels and functions.

Accepted Answer

A) risc instruction set architecture 
B) cisc instruction set architecture 
C) zisc instruction set architecture 
D) ptx instruction set architecture 
A) risc instruction set architecture 
B) cisc instruction set architecture 
C) zisc instruction set architecture 
D) ptx instruction set architecture

Question 5

What is Unified Virtual Machine

Accepted Answer

A) it is a technique that allow both cpu and gpu to read from single virtual machine, simultaneously. 
B) it is a technique for managing separate host and device memory spaces. 
C) it is a technique for executing device code on host and host code on device. 
D) it is a technique for executing general purpose programs on device instead of host. 
A) it is a technique that allow both cpu and gpu to read from single virtual machine, simultaneously. 
B) it is a technique for managing separate host and device memory spaces. 
C) it is a technique for executing device code on host and host code on device. 
D) it is a technique for executing general purpose programs on device instead of host.

Question 6

CUDA provides ------- warp and thread scheduling. Also, the overhead of thread creation is on the order of ----.

Accepted Answer

A) "programming-overhead", 2 clock 
B) "zero-overhead", 1 clock 
C) 64, 2 clock 
D) 32, 1 clock 
A) "programming-overhead", 2 clock 
B) "zero-overhead", 1 clock 
C) 64, 2 clock 
D) 32, 1 clock

Question 7

CUDA supports programming in ....

Accepted Answer

A) c or c++ only 
B) java, python, and more 
C) c, c++, third party wrappers for java, python, and more 
D) pascal 
A) c or c++ only 
B) java, python, and more 
C) c, c++, third party wrappers for java, python, and more 
D) pascal

Question 8

FADD, FMAD, FMIN, FMAX are ----- supported by Scalar Processors of NVIDIA GPU.

Accepted Answer

A) 32-bit ieee floating point instructions 
B) 32-bit integer instructions 
C) both 
D) none of the above 
A) 32-bit ieee floating point instructions 
B) 32-bit integer instructions 
C) both 
D) none of the above

Question 9

NVIDIA 8-series GPUs offer -------- .

Accepted Answer

A) 50-200 gflops 
B) 200-400 gflops 
C) 400-800 gflops 
D) 800-1000 gflops 
A) 50-200 gflops 
B) 200-400 gflops 
C) 400-800 gflops 
D) 800-1000 gflops

Question 10

CUDA stands for --------, designed by NVIDIA.

Accepted Answer

A) common union discrete architecture 
B) complex unidentified device architecture 
C) compute unified device architecture 
D) complex unstructured distributed architecture 
A) common union discrete architecture 
B) complex unidentified device architecture 
C) compute unified device architecture 
D) complex unstructured distributed architecture

Question 11

If variable a is host variable and dev_a is a device (GPU) variable, to copy input from variable a to variable dev_a select correct statement:

Accepted Answer

A) memcpy( dev_a, &a, size); 
B) cudamemcpy( dev_a, &a, size, cudamemcpyhosttodevice ); 
C) memcpy( (void*) dev_a, &a, size); 
D) cudamemcpy( (void*) &dev_a, &a, size, cudamemcpydevicetohost ); 
A) memcpy( dev_a, &a, size); 
B) cudamemcpy( dev_a, &a, size, cudamemcpyhosttodevice ); 
C) memcpy( (void*) dev_a, &a, size); 
D) cudamemcpy( (void*) &dev_a, &a, size, cudamemcpydevicetohost );

Question 12

The NVIDIA G80 is a ---- CUDA core device, the NVIDIA G200 is a ---- CUDA core device, and the NVIDIA Fermi is a ---- CUDA core device.

Accepted Answer

A) 128, 256, 512 
B) 32, 64, 128 
C) 64, 128, 256 
D) 256, 512, 1024 
A) 128, 256, 512 
B) 32, 64, 128 
C) 64, 128, 256 
D) 256, 512, 1024

Question 13

Each streaming multiprocessor (SM) of CUDA herdware has ------ scalar processors (SP).

Accepted Answer

A) 1024 
B) 128 
C) 512 
D) 8 
A) 1024 
B) 128 
C) 512 
D) 8

Question 14

Each NVIDIA GPU has ------ Streaming Multiprocessors

Accepted Answer

A) 8 
B) 1024 
C) 512 
D) 16 
A) 8 
B) 1024 
C) 512 
D) 16

Question 15

If variable a is host variable and dev_a is a device (GPU) variable, to allocate memory to dev_a select correct statement:

Accepted Answer

A) cudamalloc( &dev_a, sizeof( int ) ) 
B) malloc( &dev_a, sizeof( int ) ) 
C) cudamalloc( (void**) &dev_a, sizeof( int ) ) 
D) malloc( (void**) &dev_a, sizeof( int ) ) 
A) cudamalloc( &dev_a, sizeof( int ) ) 
B) malloc( &dev_a, sizeof( int ) ) 
C) cudamalloc( (void**) &dev_a, sizeof( int ) ) 
D) malloc( (void**) &dev_a, sizeof( int ) )

Question 16

Out-of-order instructions is not possible on GPUs.

Accepted Answer

A) True 
 B)False

Question 17

In CUDA memory model there are following memory types available:
A. Registers;
B. Local Memory;
C. Shared Memory;
D. Global Memory;
E. Constant Memory;
F. Texture Memory.

Accepted Answer

A) a, b, d, f 
B) a, c, d, e, f 
C) a, b, c, d, e, f 
D) b, c, e, f 
A) a, b, d, f 
B) a, c, d, e, f 
C) a, b, c, d, e, f 
D) b, c, e, f

Question 18

CUDA Hardware programming model supports:
A. fully generally data-parallel archtecture;
B. General thread launch;
C. Global load-store;
D. Parallel data cache;
E. Scalar architecture;
F. Integers, bit operation

Accepted Answer

A) a,c,d,f 
B) b,c,d,e 
C) a,d,e,f 
D) a,b,c,d,e,f 
A) a,c,d,f 
B) b,c,d,e 
C) a,d,e,f 
D) a,b,c,d,e,f

Question 19

A simple kernel for adding two integers:
__global__ void add( int *a, int *b, int *c ) { *c = *a + *b; }
Where __global__ is a CUDA C keyword which indicates that:

Accepted Answer

A) add() will execute on device, add() will be called from host 
B) add() will execute on host, add() will be called from device 
C) add() will be called and executed on host 
D) add() will be called and executed on device 
A) add() will execute on device, add() will be called from host 
B) add() will execute on host, add() will be called from device 
C) add() will be called and executed on host 
D) add() will be called and executed on device

Question 20

IADD, IMUL24, IMAD24, IMIN, IMAX are ----------- supported by Scalar Processors of NVIDIA GPU.

Accepted Answer

A) 32-bit ieee floating point instructions 
B) 32-bit integer instructions 
C) both 
D) none of the above 
A) 32-bit ieee floating point instructions 
B) 32-bit integer instructions 
C) both 
D) none of the above

Triple angle brackets mark in a statement inside main function, what does it indicates?

What is the equivalent of general C program with CUDA C: Int main(void) { Printf("Hello, World!\n"); Return 0; }

NVIDIA CUDA Warp is made up of how many threads?

The CUDA architecture consists of --------- for parallel computing kernels and functions.

What is Unified Virtual Machine

CUDA provides ------- warp and thread scheduling. Also, the overhead of thread creation is on the order of ----.

CUDA supports programming in ....

FADD, FMAD, FMIN, FMAX are ----- supported by Scalar Processors of NVIDIA GPU.

NVIDIA 8-series GPUs offer -------- .

CUDA stands for --------, designed by NVIDIA.

If variable a is host variable and dev_a is a device (GPU) variable, to copy input from variable a to variable dev_a select correct statement:

The NVIDIA G80 is a ---- CUDA core device, the NVIDIA G200 is a ---- CUDA core device, and the NVIDIA Fermi is a ---- CUDA core device.

Each streaming multiprocessor (SM) of CUDA herdware has ------ scalar processors (SP).

Each NVIDIA GPU has ------ Streaming Multiprocessors

If variable a is host variable and dev_a is a device (GPU) variable, to allocate memory to dev_a select correct statement:

Out-of-order instructions is not possible on GPUs.

In CUDA memory model there are following memory types available: A. Registers; B. Local Memory; C. Shared Memory; D. Global Memory; E. Constant Memory; F. Texture Memory.

CUDA Hardware programming model supports: A. fully generally data-parallel archtecture; B. General thread launch; C. Global load-store; D. Parallel data cache; E. Scalar architecture; F. Integers, bit operation

A simple kernel for adding two integers: global void add( int a, int b, int c ) { c = a + b; } Where global is a CUDA C keyword which indicates that:

IADD, IMUL24, IMAD24, IMIN, IMAX are ----------- supported by Scalar Processors of NVIDIA GPU.

Understanding Cuda Kernel Code and Host GPU Interactions

Parallel Execution in CUDA, Sorting Algorithms, and Search Techniques

Characteristics and Operations in Parallel Programming

Communication Patterns and Algorithms in Distributed Systems

Communication Operations and Algorithms in Parallel Computing

Parallel Computing and Graph Algorithms

Parallel Processing and GPU Architecture

Computer Architecture and Multiprocessor Systems

Sorting Algorithms and Pipelined Systems

Algorithms and Parallel Formulations

Cuda Model, Parallelism, Memory System, and Communication Models

Parallel Communication and Runtime Analysis

Parallel Computing and GPU Architecture

Exploring Multiprocessor Systems and Parallel Algorithms

Parallel Processing and Algorithms

Distributed Systems and Computing

Filters

Exam 2: Nvidia CUDA and GPU Programming

Triple angle brackets mark in a statement inside main function, what does it indicates?

What is the equivalent of general C program with CUDA C: Int main(void) { Printf("Hello, World!\n"); Return 0; }

NVIDIA CUDA Warp is made up of how many threads?

The CUDA architecture consists of --------- for parallel computing kernels and functions.

What is Unified Virtual Machine

CUDA provides ------- warp and thread scheduling. Also, the overhead of thread creation is on the order of ----.

CUDA supports programming in ....

FADD, FMAD, FMIN, FMAX are ----- supported by Scalar Processors of NVIDIA GPU.

NVIDIA 8-series GPUs offer -------- .

CUDA stands for --------, designed by NVIDIA.

If variable a is host variable and dev_a is a device (GPU) variable, to copy input from variable a to variable dev_a select correct statement:

The NVIDIA G80 is a ---- CUDA core device, the NVIDIA G200 is a ---- CUDA core device, and the NVIDIA Fermi is a ---- CUDA core device.

Each streaming multiprocessor (SM) of CUDA herdware has ------ scalar processors (SP).

Each NVIDIA GPU has ------ Streaming Multiprocessors

If variable a is host variable and dev_a is a device (GPU) variable, to allocate memory to dev_a select correct statement:

Out-of-order instructions is not possible on GPUs.

In CUDA memory model there are following memory types available: A. Registers; B. Local Memory; C. Shared Memory; D. Global Memory; E. Constant Memory; F. Texture Memory.

CUDA Hardware programming model supports: A. fully generally data-parallel archtecture; B. General thread launch; C. Global load-store; D. Parallel data cache; E. Scalar architecture; F. Integers, bit operation

A simple kernel for adding two integers: __global__ void add( int *a, int *b, int *c ) { *c = *a + *b; } Where __global__ is a CUDA C keyword which indicates that:

IADD, IMUL24, IMAD24, IMIN, IMAX are ----------- supported by Scalar Processors of NVIDIA GPU.

Understanding Cuda Kernel Code and Host GPU Interactions

Parallel Execution in CUDA, Sorting Algorithms, and Search Techniques

Characteristics and Operations in Parallel Programming

Communication Patterns and Algorithms in Distributed Systems

Communication Operations and Algorithms in Parallel Computing

Parallel Computing and Graph Algorithms

Parallel Processing and GPU Architecture

Computer Architecture and Multiprocessor Systems

Sorting Algorithms and Pipelined Systems

Algorithms and Parallel Formulations

Cuda Model, Parallelism, Memory System, and Communication Models

Parallel Communication and Runtime Analysis

Parallel Computing and GPU Architecture

Exploring Multiprocessor Systems and Parallel Algorithms

Parallel Processing and Algorithms

Distributed Systems and Computing

Filters

A simple kernel for adding two integers: global void add( int a, int b, int c ) { c = a + b; } Where global is a CUDA C keyword which indicates that: