Question 1

VLIW stands for:

Accepted Answer

A) vector large instruction word 
B) very long instruction word 
C) very large integrated word 
D) very low integrated word 
A) vector large instruction word 
B) very long instruction word 
C) very large integrated word 
D) very low integrated word B

Question 2

M.J. Flynn's parallel processing classification is based on:

Accepted Answer

A) multiple instructions 
B) multiple data 
C) both (a) and (b) 
D) none of the above 
A) multiple instructions 
B) multiple data 
C) both (a) and (b) 
D) none of the above C

Question 3

A Von Neumann computer uses which one of the following?

Accepted Answer

A) sisd 
B) simd 
C) misd 
D) mimd. 
A) sisd 
B) simd 
C) misd 
D) mimd. A

Question 4

A topology that involves Tokens.

Accepted Answer

A) star 
B) ring 
C) bus 
D) daisy chaining 
A) star 
B) ring 
C) bus 
D) daisy chaining

Question 5

General MIMD configuration usually called

Accepted Answer

A) a multiprocessor 
B) a vector processor 
C) array processor 
D) none of the above. 
A) a multiprocessor 
B) a vector processor 
C) array processor 
D) none of the above.

Question 6

the number of switch requirement for a network with n input and n output is ------------------

Accepted Answer

A) n 
B) n2 
C) n3 
D) n4 
A) n 
B) n2 
C) n3 
D) n4

Question 7

superscalar architecture contains -------------execution units for instruction execution

Accepted Answer

A) multiple 
B) single 
C) none of the above 
A) multiple 
B) single 
C) none of the above

Question 8

snoopy cache protocol are used in -----------------based system

Accepted Answer

A) bus 
B) mesh 
C) star 
D) hypercube 
A) bus 
B) mesh 
C) star 
D) hypercube

Question 9

Multiprocessors are classified as ________.

Accepted Answer

A) simd 
B) mimd 
C) sisd 
D) misd 
A) simd 
B) mimd 
C) sisd 
D) misd

Question 10

Which method is used as an alternative way of snooping-based coherence protocol?

Accepted Answer

A) directory protocol 
B) memory protocol 
C) compiler based protocol 
D) none of above 
A) directory protocol 
B) memory protocol 
C) compiler based protocol 
D) none of above

Question 11

MIMD stands for

Accepted Answer

A) multiple instruction multiple data 
B) multiple instruction memory data 
C) memory instruction multiple data 
D) multiple information memory data 
A) multiple instruction multiple data 
B) multiple instruction memory data 
C) memory instruction multiple data 
D) multiple information memory data

Question 12

In a three-cube structure, node 101 cannot communicate directly with node?

Accepted Answer

A) 1 
B) 11 
C) 100 
D) 111 
A) 1 
B) 11 
C) 100 
D) 111

Question 13

Which of the following is not one of the interconnection structures?

Accepted Answer

A) crossbar switch 
B) hypercube system 
C) single port memory 
D) time-shared common bus 
A) crossbar switch 
B) hypercube system 
C) single port memory 
D) time-shared common bus

Question 14

The major disadvantage of pipeline is:

Accepted Answer

A) high cost individual dedicated 
B) initial setup time 
C) if branch instruction is encountered the pipe has to be flushed 
D) all of the above 
A) high cost individual dedicated 
B) initial setup time 
C) if branch instruction is encountered the pipe has to be flushed 
D) all of the above

Question 15

How many processors can be organized in 5-dimensional binary hypercube system?

Accepted Answer

A) 25 
B) 10 
C) 32 
D) 20 
A) 25 
B) 10 
C) 32 
D) 20

Question 16

Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?

Accepted Answer

A) multiplexer 
B) decoder 
C) encoder 
D) demultiplexer 
A) multiplexer 
B) decoder 
C) encoder 
D) demultiplexer

Question 17

In super-scalar mode, all the similar instructions are grouped and executed together.

Accepted Answer

A) True 
 B)False

Question 18

MIPS stands for:

Accepted Answer

A) memory instruction per second 
B) major instruction per second 
C) main information per second 
D) million instruction per second 
A) memory instruction per second 
B) major instruction per second 
C) main information per second 
D) million instruction per second

Question 19

In super-scalar processors, ________ mode of execution is used.

Accepted Answer

A) in-order 
B) post order 
C) out of order 
D) none of the mentioned 
A) in-order 
B) post order 
C) out of order 
D) none of the mentioned

Question 20

Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?

Accepted Answer

A) directory protocol 
B) snoopy protocol 
C) server based cache coherence 
D) compiler based cache coherence 
A) directory protocol 
B) snoopy protocol 
C) server based cache coherence 
D) compiler based cache coherence

VLIW stands for:

M.J. Flynn's parallel processing classification is based on:

A Von Neumann computer uses which one of the following?

A topology that involves Tokens.

General MIMD configuration usually called

the number of switch requirement for a network with n input and n output is ------------------

superscalar architecture contains -------------execution units for instruction execution

snoopy cache protocol are used in -----------------based system

Multiprocessors are classified as ________.

Which method is used as an alternative way of snooping-based coherence protocol?

MIMD stands for

In a three-cube structure, node 101 cannot communicate directly with node?

Which of the following is not one of the interconnection structures?

The major disadvantage of pipeline is:

How many processors can be organized in 5-dimensional binary hypercube system?

Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?

In super-scalar mode, all the similar instructions are grouped and executed together.

MIPS stands for:

In super-scalar processors, ________ mode of execution is used.

Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?

Understanding Cuda Kernel Code and Host GPU Interactions

Nvidia CUDA and GPU Programming

Parallel Execution in CUDA, Sorting Algorithms, and Search Techniques

Characteristics and Operations in Parallel Programming

Communication Patterns and Algorithms in Distributed Systems

Communication Operations and Algorithms in Parallel Computing

Parallel Computing and Graph Algorithms

Parallel Processing and GPU Architecture

Sorting Algorithms and Pipelined Systems

Algorithms and Parallel Formulations

Cuda Model, Parallelism, Memory System, and Communication Models

Parallel Communication and Runtime Analysis

Parallel Computing and GPU Architecture

Exploring Multiprocessor Systems and Parallel Algorithms

Parallel Processing and Algorithms

Distributed Systems and Computing

Filters

Exam 9: Computer Architecture and Multiprocessor Systems

VLIW stands for:

M.J. Flynn's parallel processing classification is based on:

A Von Neumann computer uses which one of the following?

A topology that involves Tokens.

General MIMD configuration usually called

the number of switch requirement for a network with n input and n output is ------------------

superscalar architecture contains -------------execution units for instruction execution

snoopy cache protocol are used in -----------------based system

Multiprocessors are classified as ________.

Which method is used as an alternative way of snooping-based coherence protocol?

MIMD stands for

In a three-cube structure, node 101 cannot communicate directly with node?

Which of the following is not one of the interconnection structures?

The major disadvantage of pipeline is:

How many processors can be organized in 5-dimensional binary hypercube system?

Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?

In super-scalar mode, all the similar instructions are grouped and executed together.

MIPS stands for:

In super-scalar processors, ________ mode of execution is used.

Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?

Understanding Cuda Kernel Code and Host GPU Interactions

Nvidia CUDA and GPU Programming

Parallel Execution in CUDA, Sorting Algorithms, and Search Techniques

Characteristics and Operations in Parallel Programming

Communication Patterns and Algorithms in Distributed Systems

Communication Operations and Algorithms in Parallel Computing

Parallel Computing and Graph Algorithms

Parallel Processing and GPU Architecture

Sorting Algorithms and Pipelined Systems

Algorithms and Parallel Formulations

Cuda Model, Parallelism, Memory System, and Communication Models

Parallel Communication and Runtime Analysis

Parallel Computing and GPU Architecture

Exploring Multiprocessor Systems and Parallel Algorithms

Parallel Processing and Algorithms

Distributed Systems and Computing

Filters