Question 1

This question covers virtual memory access. Assume a 5-bit virtual address and a memory system that uses 4 bytes per page. The physical memory has 16 bytes (four page frames). The page table used is a one-level scheme that can be found in memory at the PTBR location. Initially the table indicates that no virtual pages have been mapped. Implementing a LRU page replacement algorithm, show the contents of physical memory after the following virtual accesses: 10100, 01000, 00011, 01011, 01011,11111. Show the contents of memory and the page table information after each access successfully completes in figures that follow. Also indicate when a page fault occurs. Each page table entry (PTE) is 1 byte.

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The answer of This question covers virtual memory access. Assume...

Question 2

Cache performance is of less importance in faster processors because the processor speed compensates for the high memory access time.

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A) True 
 B)False

Question 3

What needs to be stored in a branch target buffer in order to eliminate the branch penalty for an unconditional branch?
(a) Address of branch target
(b) Address of branch target and branch prediction
(c) Instruction at branch target.

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The answer of What needs to be stored in a...

Question 4

The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved.
$\bullet$Using a second-level cache
$\bullet$Using a direct-mapped cache
$\bullet$Using a 4-way set-associative cache
$\bullet$Using a virtually-addressed cache
$\bullet$Performing hardware pre-fetching using stream buffers
$\bullet$Using a non-blocking cache
$\bullet$Using larger blocks

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The answer of The Average Memory Access Time equation (AMAT)...

Question 5

A virtual cache access time is always faster than that of a physical cache?

Accepted Answer

A) True 
 B)False

Question 6

Both DRAM and SRAM must be refreshed periodically using a dummy read/write operation.

Accepted Answer

A) True 
 B)False

Question 7

Invalidation vs. Update-based Protocols.
(a) As miss latencies increase, does an update protocol become more or less preferable to an invalidation-based protocol? Explain.
(b) In a multilevel cache hierarchy, would you propagate updates all the way to the first-level cache or only to the second-level cache? Explain the trade-offs.

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The answer of Invalidation vs. Update-based Protocols.
(a) As miss latencies...

Question 8

Describe the general characteristics of a program that would exhibit very little temporal and spatial locality with regard to instruction fetches. Provide an example of such a program (pseudo- code is fine). Also, describe the cache effects of excessive unrolling. Use the terms static instructions and dynamic instructions in your description.

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The answer of Describe the general characteristics of a program...

Question 9

a. What are the two characteristics of program memory accesses that caches exploit?
b. What are three types of cache misses?
c. Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: (a)How many bits are used for the byte offset?
(b)How many bits are used for the set (index) field? (c) How many bits are used for the tag?

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The answer of a. What are the two characteristics of...

Question 10

Write the formula for the average memory access time assuming one level of cache memory:

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The answer of Write the formula for the average memory...

Question 11

Memory interleaving is a technique for reducing memory access time through increased bandwidth utilization of the data bus.

Accepted Answer

A) True 
 B)False

Question 12

Rather than a two-level page table, what other page table architecture could be used to reduce the memory foot print of page tables for the 64-bit address space from the last question? Assume that you do not need to map the full address space, but some small fraction (people typically do not have 264 bytes of physical memory). However, you should assume that the virtual pages that are mapped are uniformly distributed across the virtual address space (i.e. it is not only the low addresses or high addresses that are mapped, but rather a few pages from all ranges of memory).

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The answer of Rather than a two-level page table, what...

Question 13

The memory architecture of a machine X is summarized in the following table.
  (a) Assume that there are 8 bits reserved for the operating system functions (protection, replacement, valid, modified, and Hit/Miss- All overhead bits) other than required by the hardware translation algorithm. Derive the largest physical memory size (in bytes) allowed by this PTE format. Make sure you consider all the fields required by the translation algorithm.
(b) How large (in bytes) is the page table?
(c) Assuming 1 application exists in the system and the maximum physical memory is devoted to the process, how much physical space (in bytes) is there for the application's data and code.

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The answer of The memory architecture of a machine X...

Exam 5: Large and Fast

Cache performance is of less importance in faster processors because the processor speed compensates for the high memory access time.

What needs to be stored in a branch target buffer in order to eliminate the branch penalty for an unconditional branch? (a) Address of branch target (b) Address of branch target and branch prediction (c) Instruction at branch target.

A virtual cache access time is always faster than that of a physical cache?

Both DRAM and SRAM must be refreshed periodically using a dummy read/write operation.

Write the formula for the average memory access time assuming one level of cache memory:

Memory interleaving is a technique for reducing memory access time through increased bandwidth utilization of the data bus.