Multiple Choice
A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as____________
A) switching condition
B) master slave condition
C) race around condition
D) edge triggered condition
Correct Answer:
Verified
Correct Answer:
Verified
Q10: The main difference between a register and
Q11: A shift register is defined as_ <br>A)the register
Q12: Ripple counters are also called_ <br>A)ssi counters<br>B)asynchronous counters<br>C)synchronous
Q13: In digital logic, a counter is a
Q14: The following timing diagram shows_flip flop.<br>A)t flip-flop<br>B)d
Q16: A register that is used to store
Q17: Why do we need to define clock
Q18: A decimal counter has_states.<br>A)5<br>B)10<br>C)15<br>D)20
Q19: When both inputs of SR latches are
Q20: Which of the following sequential circuit doesn't