Question 1

Input clock of RS flip-flop is given to

Accepted Answer

A) input 
B) pulser 
C) output 
D) master slave flip-flop 
A) input 
B) pulser 
C) output 
D) master slave flip-flop B

Question 2

Master slave flip flop is also referred to as?

Accepted Answer

A) level triggered flip flop 
B) pulse triggered flip flop 
C) edge triggered flip flop 
D) edge-level triggered flip flop 
A) level triggered flip flop 
B) pulse triggered flip flop 
C) edge triggered flip flop 
D) edge-level triggered flip flop B

Question 3

The characteristic equation of D-flip-flop implies that

Accepted Answer

A) the next state is dependent on previous state 
B) the next state is dependent on present state 
C) the next state is independent of previous state 
D) the next state is independent of present state 
A) the next state is dependent on previous state 
B) the next state is dependent on present state 
C) the next state is independent of previous state 
D) the next state is independent of present state D

Question 4

At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

Accepted Answer

A) conversion condition 
B) race around condition 
C) lock out state 
D) forbidden state 
A) conversion condition 
B) race around condition 
C) lock out state 
D) forbidden state

Question 5

In a positive edge triggered JK flip flop, a low J and low K produces?

Accepted Answer

A) high state 
B) low state 
C) toggle state 
D) no change state 
A) high state 
B) low state 
C) toggle state 
D) no change state

Question 6

Which of the following is correct for a D latch?

Accepted Answer

A) the output toggles if one of the inputs is held high 
B) q output follows the input d when the enable is high 
C) only one of the inputs can be high at a time 
D) the output complement follows the input when enabled 
A) the output toggles if one of the inputs is held high 
B) q output follows the input d when the enable is high 
C) only one of the inputs can be high at a time 
D) the output complement follows the input when enabled

Question 7

Why do the D flip-flops receive its designation or nomenclature as 'Data Flip-flops'?

Accepted Answer

A) due to its capability to receive data from flip-flop 
B) due to its capability to store data in flip-flop 
C) due to its capability to transfer the data into flip-flop 
D) due to erasing the data from the flip-flop 
A) due to its capability to receive data from flip-flop 
B) due to its capability to store data in flip-flop 
C) due to its capability to transfer the data into flip-flop 
D) due to erasing the data from the flip-flop

Question 8

S-R type flip-flop can be converted into D type flip-flop if S is connected to R through

Accepted Answer

A) or gate 
B) and gate 
C) inverter 
D) full adder 
A) or gate 
B) and gate 
C) inverter 
D) full adder

Question 9

A D flip-flop can be constructed from an _ flip-flop.

Accepted Answer

A) s-r 
B) j-k 
C) t 
D) s-k 
A) s-r 
B) j-k 
C) t 
D) s-k

Question 10

Which of the following describes the operation of a positive edge-triggered D flip-flop?

Accepted Answer

A) if both inputs are high, the output will toggle 
B) the output will follow the input on the leading edge of the clock 
C) when both inputs are low, an invalid state exists 
D) the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock 
A) if both inputs are high, the output will toggle 
B) the output will follow the input on the leading edge of the clock 
C) when both inputs are low, an invalid state exists 
D) the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock

Question 11

If one wants to design a binary counter, the preferred type of flip-flop is

Accepted Answer

A) d type 
B) s-r type 
C) latch 
D) j-k type 
A) d type 
B) s-r type 
C) latch 
D) j-k type

Question 12

MOS is being used in

Accepted Answer

A) lsi 
B) vlsi 
C) msi 
D) both lsi and vlsi 
A) lsi 
B) vlsi 
C) msi 
D) both lsi and vlsi

Question 13

D flip-flop is a circuit having

Accepted Answer

A) 2 nand gates 
B) 3 nand gates 
C) 4 nand gates 
D) 5 nand gates 
A) 2 nand gates 
B) 3 nand gates 
C) 4 nand gates 
D) 5 nand gates

Question 14

A positive edge-triggered D flip-flop will store a 1 when

Accepted Answer

A) the d input is high and the clock transitions from high to low 
B) the d input is high and the clock transitions from low to high 
C) the d input is high and the clock is low 
D) the d input is high and the clock is high 
A) the d input is high and the clock transitions from high to low 
B) the d input is high and the clock transitions from low to high 
C) the d input is high and the clock is low 
D) the d input is high and the clock is high

Question 15

Which of the following is correct for a gated D flip-flop?

Accepted Answer

A) the output toggles if one of the inputs is held high 
B) only one of the inputs can be high at a time 
C) the output complement follows the input when enabled 
D) q output follows the input d when the enable is high 
A) the output toggles if one of the inputs is held high 
B) only one of the inputs can be high at a time 
C) the output complement follows the input when enabled 
D) q output follows the input d when the enable is high

Question 16

A technique used to reduce the magnitude of threshold voltage of MOSFET is the

Accepted Answer

A) use of complementary mosfet 
B) use of silicon nitride 
C) using thin film technology 
D) increasing potential of the channel 
A) use of complementary mosfet 
B) use of silicon nitride 
C) using thin film technology 
D) increasing potential of the channel

Question 17

Why MOSFET is preferred over BJT in IC components?

Accepted Answer

A) mosfet has low packing density 
B) mosfet has medium packing density 
C) mosfet has high packing density 
D) mosfet has no packing density 
A) mosfet has low packing density 
B) mosfet has medium packing density 
C) mosfet has high packing density 
D) mosfet has no packing density

Question 18

The D flip-flop has output/outputs.

Accepted Answer

A) 2 
B) 3 
C) 4 
D) 1 
A) 2 
B) 3 
C) 4 
D) 1

Question 19

In D flip-flop, if clock input is HIGH & D=1, then output is

Accepted Answer

A) 0 
B) 1 
C) forbidden 
D) toggle 
A) 0 
B) 1 
C) forbidden 
D) toggle

Question 20

Critical defects per unit chip area is for a MOS transistor.

Accepted Answer

A) high 
B) low 
C) neutral 
D) very high 
A) high 
B) low 
C) neutral 
D) very high

Input clock of RS flip-flop is given to

Master slave flip flop is also referred to as?

The characteristic equation of D-flip-flop implies that

At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

In a positive edge triggered JK flip flop, a low J and low K produces?

Which of the following is correct for a D latch?

Why do the D flip-flops receive its designation or nomenclature as 'Data Flip-flops'?

S-R type flip-flop can be converted into D type flip-flop if S is connected to R through

A D flip-flop can be constructed from an _ flip-flop.

Which of the following describes the operation of a positive edge-triggered D flip-flop?

If one wants to design a binary counter, the preferred type of flip-flop is

MOS is being used in

D flip-flop is a circuit having

A positive edge-triggered D flip-flop will store a 1 when

Which of the following is correct for a gated D flip-flop?

A technique used to reduce the magnitude of threshold voltage of MOSFET is the

Why MOSFET is preferred over BJT in IC components?

The D flip-flop has output/outputs.

In D flip-flop, if clock input is HIGH & D=1, then output is

Critical defects per unit chip area is for a MOS transistor.

Digital Circuit Design and RTL Implementation

Understanding Diode-Transistor Logic DTL and Other Logic Families

CMOS, ECL, SCFL, Lvpecl, and TTL Logic Circuits

TTL Circuits, Karnaugh Maps, and Flip-Flops

Sequential Circuits and Logic Gat

Flip-Flops, Adders, and Subtractors

Registers, Shift Registers, and Adders

Exploring Concepts and Applications of Memory and Counters in Digital Electronics

Counters and Shift Registers

Proms and Memory Addressing

Binary Arithmetic and Multiplexers/Demultiplexers

Flip-Flops, Shift Operators, and Finite State Machines Fsm in VHDL

Shift Registers, Packages, and Combinational Circuits in VHDL

Filters

Exam 6: Flip-Flops and Mosfets in IC Components

Input clock of RS flip-flop is given to

Master slave flip flop is also referred to as?

The characteristic equation of D-flip-flop implies that

At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

In a positive edge triggered JK flip flop, a low J and low K produces?

Which of the following is correct for a D latch?

Why do the D flip-flops receive its designation or nomenclature as 'Data Flip-flops'?

S-R type flip-flop can be converted into D type flip-flop if S is connected to R through

A D flip-flop can be constructed from an _ flip-flop.

Which of the following describes the operation of a positive edge-triggered D flip-flop?

If one wants to design a binary counter, the preferred type of flip-flop is

MOS is being used in

D flip-flop is a circuit having

A positive edge-triggered D flip-flop will store a 1 when

Which of the following is correct for a gated D flip-flop?

A technique used to reduce the magnitude of threshold voltage of MOSFET is the

Why MOSFET is preferred over BJT in IC components?

The D flip-flop has output/outputs.

In D flip-flop, if clock input is HIGH & D=1, then output is

Critical defects per unit chip area is for a MOS transistor.

Digital Circuit Design and RTL Implementation

Understanding Diode-Transistor Logic DTL and Other Logic Families

CMOS, ECL, SCFL, Lvpecl, and TTL Logic Circuits

TTL Circuits, Karnaugh Maps, and Flip-Flops

Sequential Circuits and Logic Gat

Flip-Flops, Adders, and Subtractors

Registers, Shift Registers, and Adders

Exploring Concepts and Applications of Memory and Counters in Digital Electronics

Counters and Shift Registers

Proms and Memory Addressing

Binary Arithmetic and Multiplexers/Demultiplexers

Flip-Flops, Shift Operators, and Finite State Machines Fsm in VHDL

Shift Registers, Packages, and Combinational Circuits in VHDL

Filters