Question 1

Exceeding the fan- out capability of a specific TTL series can cause:

Accepted Answer

A)  IOL and IOH to exceed their maximum values, forcing VOL to exceed its maximum rated value and VOH to fall below its minimum rated value. 
B)  IOL and IOH to exceed their maximum values, forcing VOL to fall below its minimum rated value and VOH to exceed its maximum rated value. 
A)  IOL and IOH to exceed their maximum values, forcing VOL to exceed its maximum rated value and VOH to fall below its minimum rated value. 
B)  IOL and IOH to exceed their maximum values, forcing VOL to fall below its minimum rated value and VOH to exceed its maximum rated value.

Question 2

When open collector outputs are wired together, the______ function is performed.

Accepted Answer

A)  OR 
B)  AND 
C)  INVERSION 
D)  NAND 
A)  OR 
B)  AND 
C)  INVERSION 
D)  NAND

Question 3

When CMOS logic circuits are driving TTL logic circuits, any current mismatch problems can usually be overcome by the addition of:

Accepted Answer

A)  a CMOS noninverting bilateral switch between the stages. 
B)  a TTL tri- state noninverting buffer between the stages. 
C)  a TTL tri- state inverting buffer between the stages. 
D)  a CMOS inverting bilateral switch between the stages. 
A)  a CMOS noninverting bilateral switch between the stages. 
B)  a TTL tri- state noninverting buffer between the stages. 
C)  a TTL tri- state inverting buffer between the stages. 
D)  a CMOS inverting bilateral switch between the stages.

Question 4

Which of the following is a disadvantage of a totem- pole output?

Accepted Answer

A)  When switching from HIGH to LOW, Q4 is changing from saturation to cutoff. This transition takes longer than Q3's transition so for a short period a surge of current is drawn from Vcc. 
B)  When switching LOW to HIGH, Q3 is changing from saturation to cutoff. This transition takes longer than Q4's transition so for a short period a surge current is drawn from Vcc. 
C)  When switching from LOW to HIGH, Q4 is changing from saturation to cutoff. This transition takes longer than Q3's transition so for a short period a surge of current is drawn from Vcc. 
D)  Both A and C 
A)  When switching from HIGH to LOW, Q4 is changing from saturation to cutoff. This transition takes longer than Q3's transition so for a short period a surge of current is drawn from Vcc. 
B)  When switching LOW to HIGH, Q3 is changing from saturation to cutoff. This transition takes longer than Q4's transition so for a short period a surge current is drawn from Vcc. 
C)  When switching from LOW to HIGH, Q4 is changing from saturation to cutoff. This transition takes longer than Q3's transition so for a short period a surge of current is drawn from Vcc. 
D)  Both A and C

Exceeding the fan- out capability of a specific TTL series can cause:

When open collector outputs are wired together, the______ function is performed.

When CMOS logic circuits are driving TTL logic circuits, any current mismatch problems can usually be overcome by the addition of:

Which of the following is a disadvantage of a totem- pole output?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 8: Integrated-Circuit Logic Families

Exceeding the fan- out capability of a specific TTL series can cause:

When open collector outputs are wired together, the______ function is performed.

When CMOS logic circuits are driving TTL logic circuits, any current mismatch problems can usually be overcome by the addition of:

Which of the following is a disadvantage of a totem- pole output?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters