Question 1

A PLD is an IC that contains large numbers of gates, FFs, and registers that are often interconnected by fusible links.

Accepted Answer

A) True 
 B)False  True

Question 2

In the MAX7000s family, the number of I/O pins is determined by ______.

Accepted Answer

the device package

Question 3

Universal programmers can program any type of device EXCEPT EPROMS.

Accepted Answer

A) True 
 B)False  False

Question 4

In the variable DECODE.OE the OE is a(n):

Accepted Answer

A)  extension. 
B)  variable name. 
C)  expression. 
D)  state name. 
A)  extension. 
B)  variable name. 
C)  expression. 
D)  state name.

Question 5

A fuse _____ file shows the actual fuse pattern that will be burned into the PLD.

Accepted Answer

The answer of A fuse _____ file shows the actual...

Question 6

GALs contain optional flip- flops for______.

Accepted Answer

register a

Question 7

The four input- only pins found on MAX7000s devices can be configured as general user inputs or as______.

Accepted Answer

high- spee

Question 8

Each MAX II device contains CFM and UFM. These are_____.

Accepted Answer

The answer of Each MAX II device contains CFM and...

Question 9

The major structures in the MAX7000s are the LABs and the_____.

Accepted Answer

The answer of The major structures in the MAX7000s are...

Question 10

Which of the following best describes PLD PROM architecture?

Accepted Answer

A)  The inputs to the AND array and the product line inputs to the OR gates are both programmable. 
B)  The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable. 
C)  The inputs to the AND array and the product line inputs to the OR gates are both hard- wired. 
D)  The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired. 
A)  The inputs to the AND array and the product line inputs to the OR gates are both programmable. 
B)  The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable. 
C)  The inputs to the AND array and the product line inputs to the OR gates are both hard- wired. 
D)  The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired.

Question 11

What advantage do GAL devices have over PAL devices other than the ability to be reprogrammed?

Accepted Answer

A)  The output macrocell 
B)  AND/OR arrays 
C)  They are cheaper 
D)  PIAs 
A)  The output macrocell 
B)  AND/OR arrays 
C)  They are cheaper 
D)  PIAs

Question 12

Whenever a MAX II device is powered up, it is necessary to load the LUT memory for the desired functions. This is because the SRAM is____	.

Accepted Answer

The answer of Whenever a MAX II device is powered...

Question 13

The "dot" in a PLD diagram represents:

Accepted Answer

A)  an open connection. 
B)  a programmable point. 
C)  a hard- wired connection. 
D)  an intact fuse. 
A)  an open connection. 
B)  a programmable point. 
C)  a hard- wired connection. 
D)  an intact fuse.

Question 14

A blown input to an AND gate in a PLD would normally be held:

Accepted Answer

A)  tri- state. 
B)  LOW. 
C)  invalid. 
D)  HIGH. 
A)  tri- state. 
B)  LOW. 
C)  invalid. 
D)  HIGH.

Question 15

The major difference in architecture between MAX7000s devices and MAX II devices is_______

Accepted Answer

the MAX II devices u

Question 16

The first step in the development cycle results in the labeling of all inputs and outputs.

Accepted Answer

A) True 
 B)False

Question 17

Software development packages can be classified as either ____ level development systems or______ level logic compilers.

Accepted Answer

The answer of Software development packages can be classified as...

Question 18

MAX II architecture has 10 logic elements arranged together into a_____

Accepted Answer

logic arra

Question 19

Most PLD programmers use a_____socket to hold the device.

Accepted Answer

The answer of Most PLD programmers use a_____socket to hold...

Question 20

Which of the following best describes typical PAL architecture?

Accepted Answer

A)  The inputs to the AND array and the product line inputs to the OR gates are both hard- wired. 
B)  The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired. 
C)  The inputs to the AND array and the product line inputs to the OR gates are both programmable. 
D)  The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable. 
A)  The inputs to the AND array and the product line inputs to the OR gates are both hard- wired. 
B)  The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired. 
C)  The inputs to the AND array and the product line inputs to the OR gates are both programmable. 
D)  The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable.

A PLD is an IC that contains large numbers of gates, FFs, and registers that are often interconnected by fusible links.

In the MAX7000s family, the number of I/O pins is determined by ______.

Universal programmers can program any type of device EXCEPT EPROMS.

In the variable DECODE.OE the OE is a(n):

A fuse _____ file shows the actual fuse pattern that will be burned into the PLD.

GALs contain optional flip- flops for______.

The four input- only pins found on MAX7000s devices can be configured as general user inputs or as______.

Each MAX II device contains CFM and UFM. These are_____.

The major structures in the MAX7000s are the LABs and the_____.

Which of the following best describes PLD PROM architecture?

What advantage do GAL devices have over PAL devices other than the ability to be reprogrammed?

Whenever a MAX II device is powered up, it is necessary to load the LUT memory for the desired functions. This is because the SRAM is____ .

The "dot" in a PLD diagram represents:

A blown input to an AND gate in a PLD would normally be held:

The major difference in architecture between MAX7000s devices and MAX II devices is_______

The first step in the development cycle results in the labeling of all inputs and outputs.

Software development packages can be classified as either level development systems or__ level logic compilers.

MAX II architecture has 10 logic elements arranged together into a_____

Most PLD programmers use a_____socket to hold the device.

Which of the following best describes typical PAL architecture?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Filters

Exam 13: Programmable Logic Device Architectures

A PLD is an IC that contains large numbers of gates, FFs, and registers that are often interconnected by fusible links.

In the MAX7000s family, the number of I/O pins is determined by ______.

Universal programmers can program any type of device EXCEPT EPROMS.

In the variable DECODE.OE the OE is a(n):

A fuse _____ file shows the actual fuse pattern that will be burned into the PLD.

GALs contain optional flip- flops for______.

The four input- only pins found on MAX7000s devices can be configured as general user inputs or as______.

Each MAX II device contains CFM and UFM. These are_____.

The major structures in the MAX7000s are the LABs and the_____.

Which of the following best describes PLD PROM architecture?

What advantage do GAL devices have over PAL devices other than the ability to be reprogrammed?

Whenever a MAX II device is powered up, it is necessary to load the LUT memory for the desired functions. This is because the SRAM is____ .

The "dot" in a PLD diagram represents:

A blown input to an AND gate in a PLD would normally be held:

The major difference in architecture between MAX7000s devices and MAX II devices is_______

The first step in the development cycle results in the labeling of all inputs and outputs.

Software development packages can be classified as either ____ level development systems or______ level logic compilers.

MAX II architecture has 10 logic elements arranged together into a_____

Most PLD programmers use a_____socket to hold the device.

Which of the following best describes typical PAL architecture?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Filters

Software development packages can be classified as either level development systems or__ level logic compilers.