Exam 5: Flip-Flops and Related Devices
Exam 1: Introductory Concepts69 Questions
Exam 2: Number Systems and Codes81 Questions
Exam 3: Describing Logic Circuits92 Questions
Exam 4: Combinational Logic Circuits81 Questions
Exam 5: Flip-Flops and Related Devices80 Questions
Exam 6: Digital Arithmetic: Operations and Circuits74 Questions
Exam 7: Counters and Registers75 Questions
Exam 8: Integrated-Circuit Logic Families104 Questions
Exam 9: MSI Logic Circuits78 Questions
Exam 10: Digital System Projects Using HDL77 Questions
Exam 11: Interfacing With the Analog World91 Questions
Exam 12: Memory Devices116 Questions
Exam 13: Programmable Logic Device Architectures41 Questions
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Generally, a flip- flop's hold- time is short enough to allow its output to be determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
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(True/False)
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Correct Answer:
True
Which of the following circuit parameters would be most likely to limit the maximum operating frequency of an IC flip- flop?
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(Multiple Choice)
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Correct Answer:
B
The difference between a D- latch and an edge- triggered D- type flip- flop is that the latch:
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Correct Answer:
A
Which statement best describes the action of a NAND gate latch?
(Multiple Choice)
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Which of the following flip- flop timing parameters indicates the time it takes a Q output to respond to an input?
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A small triangle at the CLK input on a standard flip- flop symbol indicates that any change in the output is triggered by a clock transition.
(True/False)
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A "D" flip- flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
(Multiple Choice)
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Which of the following statements regarding the small triangles in the IEEE/ANSI symbols for flip- flops is TRUE?
(Multiple Choice)
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A one- shot has a stable output state that is essentially interrupted by the trigger input. Once interrupted, the output goes to the opposite state for a specific amount of time.
(True/False)
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Forcing the SET input LOW on a NAND gate latch generates outputs of:
(Multiple Choice)
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A primary difference between a D flip- flop and the J- K and S- C flip- flops is the fact that:
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Which of the following logic devices is specifically designed to produce clean, fast- changing output signals?
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What is the output frequency of a three- stage binary counter with an input clock frequency of 80 kHz?
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74xxx standard logic chips are found in the megafunction library of the Quartus II development software.
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Which of the following best describes the normal logical operation of a NOR gate latch?
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The new IEEE/ANSI symbols for latches and flip- flop use the letter "C" to denote:
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A_____accepts slow- changing input signals and generates clean, fast- transition output signals.
(Short Answer)
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The Q output of a flip- flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.
(True/False)
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Which of the following best describes the characteristics of a MOD- 16 counter?
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