Exam 12: Memory Devices

FIFO memory operations are controlled by special address ______registers that keep track of where data is to be written and from where it is to be read.

A 16 K × 8 memory module can be made from four 8 K × 1 chips.

A burst refresh and normal memory operation of a DRAM can be interspersed.

Modern hard drives store data by______of the medium.

Which type of memory cell would normally be associated with a "sense" amplifier?

A FIFO can be used as a______ buffer between a slow device and a computer.

A ROM IC chip normally has a read/write control input.

Memory enable, chip enable, and chip select are terms used to describe a memory function that will completely disable all or part of the memory so that it will not respond to other inputs.

______memories are so called because of their rapid erase and write times.

Which of the following memory devices comes with a window?

An______is user programmable and can also be erased electronically and reprogrammed as often as desired.

Which of the following lists memory devices from the most complex and expensive, to the least complex and expensive?

How many address lines would be required for a 4 K × 4 memory?

Which of the following memories are sequential- access devices?

Most ROM ICs have tri- state outputs that:

A DRAM chip has______and______inputs instead of a chip select input.

What two functions does a DRAM controller perform?

How many bits of information could normally be stored in a memory device with a capacity of 256 K?

Which of the following terms best describes Read- Only- Memory (ROM)?

How many 1 K × 4 chips would be required to produce an 8 K × 16 module?