Exam 13: Programmable Logic Device Architectures

Which of the following contains an EEPROM array?

When writing the logic equations in PLD development software the logic_____is placed on the right side.

The GAL devices use _______to select input terms.

For a given PLD, if none of the input to the OR gate are connected, the output of this gate will be:

What does an x represent on a PLD diagram?

The basic difference between a PROM and a PAL is that:

GAL devices are very similar to what type of devices?

Which of the following PLDs has two programmable arrays?

Which of the following refers to a PAL that has eight registered outputs plus eight dedicated inputs?

A PC, running developmental software, translates an input design into a file called a fuse_______ .

In the MAX II family, the LUTs typically handle _____ input variables.

When writing the logic equations in PLD development software the_____ is placed on the left side.

Which of the following have a programmable OR array and a programmable AND array?

A FPGA is an array of PLD cells.

The output line of an AND gate in a Programmable Logic Device is normally called a:

PLD's are programmed by_____ fuses.

Many PLD's include a programmable output____ feature that gives the designer the option to invert any of the device outputs.

Compared to the Cyclone II the Cyclone III has _____performance and_____cost.

The term ASICS is often used to describe simple PLDs.

In the MAX II series, _____provide clock frequency multiplication and division.