Exam 4: Building Blocks of Integrated-Circuit Amplifiers

Given the availability of NMOS and PMOS transistors that are matched and have $k_{n}=k_{p}=$ $5 \mathrm{~mA} / \mathrm{V}^{2}$ and $V_{A n}=-V_{A p}=5 \mathrm{~V}$ , give circuits for the following amplifiers. In each case, find the output resistance and the voltage gain. In all cases, operate each transistor at a dc bias current of $100 \mu \mathrm{A}$ and give the value of $\left|V_{O V}\right|$ at which each transistor is operating. (a) An NMOS common-source amplifier with a PMOS current-source load. (b) An NMOS common-source amplifier with an NMOS cascode stage and a single-transistor PMOS current-source load. (c) An NMOS common-source amplifier with an NMOS cascode stage and a cascode PMOS current-source load.

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Question 1

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For each transistor,
$\begin{aligned}k_{n} & =k_{p}=5 \mathrm{~mA} / \mathrm{V}^{2} \\V_{A n} & =-V_{A p}=5 \mathrm{~V} \\I_{D} & =100 \mu \mathrm{A}\end{aligned}$
$\begin{aligned}I_{D} & =\frac{1}{2} k\left|V_{O V}\right|^{2} \\0.1 & =\frac{1}{2} \times 5 \times\left|V_{O V}\right|^{2} \\\Rightarrow\left|V_{O V}\right| & =0.2 \mathrm{~V} \\g_{m} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.1}{0.2}=1 \mathrm{~mA} / \mathrm{V} \\r_{O} & =\frac{\left|V_{A}\right|}{I_{D}}=\frac{5}{0.1}=50 \mathrm{k} \Omega\end{aligned}$
(a)
$For each transistor, \begin{aligned} k_{n} & =k_{p}=5 \mathrm{~mA} / \mathrm{V}^{2} \\ V_{A n} & =-V_{A p}=5 \mathrm{~V} \\ I_{D} & =100 \mu \mathrm{A} \end{aligned} \begin{aligned} I_{D} & =\frac{1}{2} k\left|V_{O V}\right|^{2} \\ 0.1 & =\frac{1}{2} \times 5 \times\left|V_{O V}\right|^{2} \\ \Rightarrow\left|V_{O V}\right| & =0.2 \mathrm{~V} \\ g_{m} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.1}{0.2}=1 \mathrm{~mA} / \mathrm{V} \\ r_{O} & =\frac{\left|V_{A}\right|}{I_{D}}=\frac{5}{0.1}=50 \mathrm{k} \Omega \end{aligned} (a) Figure 8.2.1 See Figure 8.2.1. \begin{aligned} & R_{o}=r_{o n}\left\|r_{o p}=50\right\| 50=25 \mathrm{k} \Omega \\ & A_{V}=-g_{m} R_{O}=-1 \times 25=-25 \mathrm{~V} / \mathrm{V} \end{aligned} (b) Figure 8.2.2 \begin{aligned} R_{O 2} & \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} \\ & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} & =r_{o 3}=50 \mathrm{k} \Omega \\ R_{O} & =R_{O 2}\left\|R_{O 3}=50\right\| 2500=49 \mathrm{k} \Omega \\ A_{v} & =-g_{m 1} R_{O}=-1 \times 49=-49 \mathrm{~V} / \mathrm{V} \end{aligned} (c) Figure 8.2.3 \begin{aligned} R_{o 2} \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} \simeq\left(g_{m 3} r_{o 3}\right) r_{o 4} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O}=R_{O 2} \| R_{O 3} & =2500 \| 2500=1250 \mathrm{k} \Omega \\ A_{v}=-g_{m 1} R_{O} & =-1 \times 1250=-1250 \mathrm{~V} / \mathrm{V} \end{aligned}$
Figure 8.2.1
See Figure 8.2.1.
$\begin{aligned}& R_{o}=r_{o n}\left\|r_{o p}=50\right\| 50=25 \mathrm{k} \Omega \\& A_{V}=-g_{m} R_{O}=-1 \times 25=-25 \mathrm{~V} / \mathrm{V}\end{aligned}$
(b)
$For each transistor, \begin{aligned} k_{n} & =k_{p}=5 \mathrm{~mA} / \mathrm{V}^{2} \\ V_{A n} & =-V_{A p}=5 \mathrm{~V} \\ I_{D} & =100 \mu \mathrm{A} \end{aligned} \begin{aligned} I_{D} & =\frac{1}{2} k\left|V_{O V}\right|^{2} \\ 0.1 & =\frac{1}{2} \times 5 \times\left|V_{O V}\right|^{2} \\ \Rightarrow\left|V_{O V}\right| & =0.2 \mathrm{~V} \\ g_{m} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.1}{0.2}=1 \mathrm{~mA} / \mathrm{V} \\ r_{O} & =\frac{\left|V_{A}\right|}{I_{D}}=\frac{5}{0.1}=50 \mathrm{k} \Omega \end{aligned} (a) Figure 8.2.1 See Figure 8.2.1. \begin{aligned} & R_{o}=r_{o n}\left\|r_{o p}=50\right\| 50=25 \mathrm{k} \Omega \\ & A_{V}=-g_{m} R_{O}=-1 \times 25=-25 \mathrm{~V} / \mathrm{V} \end{aligned} (b) Figure 8.2.2 \begin{aligned} R_{O 2} & \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} \\ & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} & =r_{o 3}=50 \mathrm{k} \Omega \\ R_{O} & =R_{O 2}\left\|R_{O 3}=50\right\| 2500=49 \mathrm{k} \Omega \\ A_{v} & =-g_{m 1} R_{O}=-1 \times 49=-49 \mathrm{~V} / \mathrm{V} \end{aligned} (c) Figure 8.2.3 \begin{aligned} R_{o 2} \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} \simeq\left(g_{m 3} r_{o 3}\right) r_{o 4} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O}=R_{O 2} \| R_{O 3} & =2500 \| 2500=1250 \mathrm{k} \Omega \\ A_{v}=-g_{m 1} R_{O} & =-1 \times 1250=-1250 \mathrm{~V} / \mathrm{V} \end{aligned}$

Figure 8.2.2
$\begin{aligned}R_{O 2} & \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} \\& =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\R_{O 3} & =r_{o 3}=50 \mathrm{k} \Omega \\R_{O} & =R_{O 2}\left\|R_{O 3}=50\right\| 2500=49 \mathrm{k} \Omega \\A_{v} & =-g_{m 1} R_{O}=-1 \times 49=-49 \mathrm{~V} / \mathrm{V}\end{aligned}$
(c)
$For each transistor, \begin{aligned} k_{n} & =k_{p}=5 \mathrm{~mA} / \mathrm{V}^{2} \\ V_{A n} & =-V_{A p}=5 \mathrm{~V} \\ I_{D} & =100 \mu \mathrm{A} \end{aligned} \begin{aligned} I_{D} & =\frac{1}{2} k\left|V_{O V}\right|^{2} \\ 0.1 & =\frac{1}{2} \times 5 \times\left|V_{O V}\right|^{2} \\ \Rightarrow\left|V_{O V}\right| & =0.2 \mathrm{~V} \\ g_{m} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.1}{0.2}=1 \mathrm{~mA} / \mathrm{V} \\ r_{O} & =\frac{\left|V_{A}\right|}{I_{D}}=\frac{5}{0.1}=50 \mathrm{k} \Omega \end{aligned} (a) Figure 8.2.1 See Figure 8.2.1. \begin{aligned} & R_{o}=r_{o n}\left\|r_{o p}=50\right\| 50=25 \mathrm{k} \Omega \\ & A_{V}=-g_{m} R_{O}=-1 \times 25=-25 \mathrm{~V} / \mathrm{V} \end{aligned} (b) Figure 8.2.2 \begin{aligned} R_{O 2} & \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} \\ & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} & =r_{o 3}=50 \mathrm{k} \Omega \\ R_{O} & =R_{O 2}\left\|R_{O 3}=50\right\| 2500=49 \mathrm{k} \Omega \\ A_{v} & =-g_{m 1} R_{O}=-1 \times 49=-49 \mathrm{~V} / \mathrm{V} \end{aligned} (c) Figure 8.2.3 \begin{aligned} R_{o 2} \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O 3} \simeq\left(g_{m 3} r_{o 3}\right) r_{o 4} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\ R_{O}=R_{O 2} \| R_{O 3} & =2500 \| 2500=1250 \mathrm{k} \Omega \\ A_{v}=-g_{m 1} R_{O} & =-1 \times 1250=-1250 \mathrm{~V} / \mathrm{V} \end{aligned}$

Figure 8.2.3
$\begin{aligned}R_{o 2} \simeq\left(g_{m 2} r_{o 2}\right) r_{o 1} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\R_{O 3} \simeq\left(g_{m 3} r_{o 3}\right) r_{o 4} & =(1 \times 50) \times 50=2500 \mathrm{k} \Omega \\R_{O}=R_{O 2} \| R_{O 3} & =2500 \| 2500=1250 \mathrm{k} \Omega \\A_{v}=-g_{m 1} R_{O} & =-1 \times 1250=-1250 \mathrm{~V} / \mathrm{V}\end{aligned}$

$Figure 8.4.1 The cascode current source in Fig. 8.4.1 utilizes two identical PMOS transistors fabricated in a 0.18 - \mu \mathrm{m} CMOS process for which V_{D D}=1.8 \mathrm{~V} , V_{t p}=-0.5 \mathrm{~V}, V_{A}^{\prime}=-6 \mathrm{~V} / \mu \mathrm{m} , and \mu_{p} C_{o x}= 100 \mu \mathrm{A} / \mathrm{V}^{2} . Design the circuit to obtain I=50 \mu \mathrm{A} and R_{O}=1 \mathrm{M} \Omega and to allow for the maximum possible voltage swing at the output terminal of the current source. Utilize \left|V_{O V}\right|=0.2 \mathrm{~V} . Specify the values of L and W / L for Q_{1} and Q_{2} . As well, specify the required values of the dc bias voltages V_{G 1} and V_{G 2} . What is the maximum allowable voltage at the output?$ Figure 8.4.1 The cascode current source in Fig. 8.4.1 utilizes two identical PMOS transistors fabricated in a 0.18 - $\mu \mathrm{m}$ CMOS process for which $V_{D D}=1.8 \mathrm{~V}$ , $V_{t p}=-0.5 \mathrm{~V}, V_{A}^{\prime}=-6 \mathrm{~V} / \mu \mathrm{m}$ , and $\mu_{p} C_{o x}=$ $100 \mu \mathrm{A} / \mathrm{V}^{2}$ . Design the circuit to obtain $I=50 \mu \mathrm{A}$ and $R_{O}=1 \mathrm{M} \Omega$ and to allow for the maximum possible voltage swing at the output terminal of the current source. Utilize $\left|V_{O V}\right|=0.2 \mathrm{~V}$ . Specify the values of $L$ and $W / L$ for $Q_{1}$ and $Q_{2}$ . As well, specify the required values of the dc bias voltages $V_{G 1}$ and $V_{G 2}$ . What is the maximum allowable voltage at the output?

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Question 2

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$Figure 8.4.2 \begin{aligned} V_{S G} & =\left|V_{t p}\right|+\left|V_{O V}\right| \\ & =0.5+0.2=0.7 \mathrm{~V} \end{aligned} Minimum required voltage V_{S D}=\left|V_{O V}\right|=0.2 \mathrm{~V} . From Fig. 8.4.2, we see that \begin{aligned} V_{G 1} & =+0.9 \mathrm{~V} \\ V_{G 2} & =+1.1 \mathrm{~V} \\ v_{O \max } & =+0.9+0.5=1.4 \mathrm{~V} \\ I_{D} & =\frac{1}{2}\left(\mu_{p} C_{o x}\right)\left(\frac{W}{L}\right)\left|V_{O V}\right|^{2} \\ 50 & =\frac{1}{2} \times 100 \times \frac{W}{L} \times 0.2^{2} \\ \Rightarrow \frac{W}{L} & =25 \\ R_{o} & =R_{o 1}=\left(g_{m 1} r_{o 1}\right) r_{o 2} \end{aligned} where \begin{aligned} g_{m 1} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.05}{0.2}=0.5 \mathrm{~mA} / \mathrm{V} \\ r_{o 1} & =r_{o 2}=\frac{\left|V_{A}\right|}{I_{D}}=\frac{\left|V_{A}^{\prime}\right| L}{I_{D}} \end{aligned} For R_{O}=1 \mathrm{M} \Omega , \begin{aligned} 1000 & =0.5 r_{o}^{2} \\ \Rightarrow r_{o} & =44.72 \mathrm{k} \Omega \\ 44.72 & =\frac{6 L}{0.05} \\ \Rightarrow L & =0.37 \mu \mathrm{m} \end{aligned}$
Figure 8.4.2
$\begin{aligned}V_{S G} & =\left|V_{t p}\right|+\left|V_{O V}\right| \\& =0.5+0.2=0.7 \mathrm{~V}\end{aligned}$
Minimum required voltage $V_{S D}=\left|V_{O V}\right|=0.2 \mathrm{~V}$ .
From Fig. 8.4.2, we see that
$\begin{aligned}V_{G 1} & =+0.9 \mathrm{~V} \\V_{G 2} & =+1.1 \mathrm{~V} \\v_{O \max } & =+0.9+0.5=1.4 \mathrm{~V} \\I_{D} & =\frac{1}{2}\left(\mu_{p} C_{o x}\right)\left(\frac{W}{L}\right)\left|V_{O V}\right|^{2} \\50 & =\frac{1}{2} \times 100 \times \frac{W}{L} \times 0.2^{2} \\\Rightarrow \frac{W}{L} & =25 \\R_{o} & =R_{o 1}=\left(g_{m 1} r_{o 1}\right) r_{o 2}\end{aligned}$
where
$\begin{aligned}g_{m 1} & =\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.05}{0.2}=0.5 \mathrm{~mA} / \mathrm{V} \\r_{o 1} & =r_{o 2}=\frac{\left|V_{A}\right|}{I_{D}}=\frac{\left|V_{A}^{\prime}\right| L}{I_{D}}\end{aligned}$
For $R_{O}=1 \mathrm{M} \Omega$ ,
$\begin{aligned}1000 & =0.5 r_{o}^{2} \\\Rightarrow r_{o} & =44.72 \mathrm{k} \Omega \\44.72 & =\frac{6 L}{0.05} \\\Rightarrow L & =0.37 \mu \mathrm{m}\end{aligned}$

$Figure 8.1.1 For the circuit shown in Fig. 8.1.1, assume Q_{1} and Q_{2} are perfectly matched, and Q_{3}, Q_{4} , and Q_{5} are perfectly matched. Also, assume all transistors have very high \beta and V_{A} . Find V_{1}, I , and V_{2} .$ Figure 8.1.1 For the circuit shown in Fig. 8.1.1, assume $Q_{1}$ and $Q_{2}$ are perfectly matched, and $Q_{3}, Q_{4}$ , and $Q_{5}$ are perfectly matched. Also, assume all transistors have very high $\beta$ and $V_{A}$ . Find $V_{1}, I$ , and $V_{2}$ .

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Question 3

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Figure 8.1.2
The analysis is shown on Fig. 8.1.2.

$Figure 8.3.1 Design the double-cascode current source shown in Fig. 8.3.1 to provide I=0.2 \mathrm{~mA} and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The CMOS fabrication process available has \left|V_{t p}\right|=0.4 \mathrm{~V},\left|V_{A}^{\prime}\right|=6 \mathrm{~V} / \mu \mathrm{m} , and \mu_{p} C_{o x}=100 \mu \mathrm{A} / \mathrm{V}^{2} . Use devices with L= 0.4 \mu \mathrm{m} , and operate at \left|V_{O V}\right|=0.2 \mathrm{~V} . (a) Specify V_{G 1}, V_{G 2} , and V_{G 3} . (b) Find the W / L ratios of the transistors. (c) What is the value of R_{O} achieved? (d) What is the maximum allowable voltage at the current-source output? (e) If this current source is used as the load of an NMOS double-cascode amplifier having a shortcircuit transconductance of 2 \mathrm{~mA} / \mathrm{V} and an output resistance equal to R_{O} of the current source, what voltage gain is obtained?$ Figure 8.3.1 Design the double-cascode current source shown in Fig. 8.3.1 to provide $I=0.2 \mathrm{~mA}$ and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The CMOS fabrication process available has $\left|V_{t p}\right|=0.4 \mathrm{~V},\left|V_{A}^{\prime}\right|=6 \mathrm{~V} / \mu \mathrm{m}$ , and $\mu_{p} C_{o x}=100 \mu \mathrm{A} / \mathrm{V}^{2}$ . Use devices with $L=$ $0.4 \mu \mathrm{m}$ , and operate at $\left|V_{O V}\right|=0.2 \mathrm{~V}$ . (a) Specify $V_{G 1}, V_{G 2}$ , and $V_{G 3}$ . (b) Find the $W / L$ ratios of the transistors. (c) What is the value of $R_{O}$ achieved? (d) What is the maximum allowable voltage at the current-source output? (e) If this current source is used as the load of an NMOS double-cascode amplifier having a shortcircuit transconductance of $2 \mathrm{~mA} / \mathrm{V}$ and an output resistance equal to $R_{O}$ of the current source, what voltage gain is obtained?

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Question 4

$Figure 8.5.1 The modified Wilson current mirror of Fig. 8.5.1 utilizes four matched transistors for which V_{t}= 0.4 \mathrm{~V}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2} , and V_{A}=3 \mathrm{~V} . It is required to design the circuit so that I_{O}=0.2 \mathrm{~mA} with all transistors operating at V_{O V}=0.2 \mathrm{~V} . (a) Find the required value of R . (b) Find the required value of the W / L ratio for each of the four transistors. (c) Find the value of the output resistance R_{O} . (d) What is the minimum voltage permitted at the output?$ Figure 8.5.1 The modified Wilson current mirror of Fig. 8.5.1 utilizes four matched transistors for which $V_{t}=$ $0.4 \mathrm{~V}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2}$ , and $V_{A}=3 \mathrm{~V}$ . It is required to design the circuit so that $I_{O}=0.2 \mathrm{~mA}$ with all transistors operating at $V_{O V}=0.2 \mathrm{~V}$ . (a) Find the required value of $R$ . (b) Find the required value of the $W / L$ ratio for each of the four transistors. (c) Find the value of the output resistance $R_{O}$ . (d) What is the minimum voltage permitted at the output?

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