Exam 8: Operational Amplifier Circuits, Filters, Oscillators and CMOS Digital Logic Circuits
Figure 14.1.1
It is required to design a fifth-order Butterworth low-pass filter with a de gain of unity, a passband edge of , and a maximum deviation in the passband transmission of (i.e., ).
(a) Find the transfer function and give and of each of the two pairs of complex-conjugate poles. Also, specify the frequency of the real pole.
(b) Provide a complete circuit realization of the filter as a cascade of two second-order sections and a first-order section. For the second-order sections, use realizations based on the inductancesimulation circuit of Fig. 14.1.1. For the first-order section, use an op amp-RC circuit. Design so that all capacitors are equal to and as many of the resistors as possible are equal. Give the complete circuit and specify the values of all resistors.
(c) What is the attenuation achieved at the stopband edge, ?

(a)
Figure 14.1.2
Figure 14.1.2 shows the -plane locations of the poles. Here,
The pair of complex-conjugate poles and have
and
The pair of complex-conjugate poles and have
and
The real pole has a frequency
Thus, the transfer function of the fifth-order lowpass filter is
where the numerator was found by enforcing the condition
(b) Refer to Figure 14.1.3
Figure 14.1.3
Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,
For the circuit realizing ,
For the circuit realizing ,
Each circuit has a unity de gain.
Figure 14.1.4
Figure 14.1.4 shows the circuit for realizing the real-axis pole, . Here
The feedback resistance is selected equal to so as to obtain a unity de gain.
Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5
(c)
where
At ,
Figure 14.1.6
Figure 16.3.1
The CMOS inverter shown in Fig. 16.3.1 is fabricated in a technology having , , and .
(a) Find to obtain matched transistors.
(b) For , find the maximum load current that the inverter can sink while is not exceeding .

(a) For matching,
(b) For will be operating in the triode region:
For ,
The CMOS inverter shown in Fig. 16.2.1 has and is fabricated in a process for which , and . For this problem, neglect the Early effect. Both and use the minimum channel length allowed. For .
(a) Find the dimensions that must have in order for the inverter switching to occur at .
(b) What are the noise margins of the inverter?
(c) What current flows in and at the switching point?
(d) For , what is the maximum current that can sink while is limited to ?

Figure 16.2.1
(a) For the inverter switching to occur at , which is and must be matched:
Thus,
Since and
we obtain
(b)
(c) At the switching point, and operate in saturation:
(d) For is operating in the triode region:
For and ,
Figure 16.1.1
(a) For the CMOS inverter in Fig. 16.1.1, and have and . Sketch and clearly label the VTC versus and give values for the noise margins and . What is the output resistance when ?
(b) Provide the CMOS realization of the logic function.

Figure 13.2.1
It is required to design the folded-cascode op amp shown in Fig. 13.2.1. Let and , and assume that for all transistors, . Design so that the power dissipated in the circuit (with no input signal applied) is , and so that each of and is operating at a current four times that at which each of and is operating. Also, design so that all transistors operate at .
(a) Show that the current drawn from each of the two power supplies is , and hence find and that result in the circuit operating at its specified power dissipation.
(b) Find the dc current at which each of to is operating. Present your results in a table.
(c) Find the input common-mode range.
(d) Find the required values of , and that result in the maximum allowable value of to be as high as possible.
(e) Find the allowable range of .
(f) Find the overall transconductance .
(g) Find the output resistance .
(h) Find the low-frequency voltage gain.
(i) If the amplifier at its output is modeled by a controlled current-source (where is the differential input voltage) feeding the output resistance and the total capacitance at the output node , find the value of that results in the amplifier having a unity-gain bandwidth of . Assume that the dominant pole is that formed at the output.

In the cross-coupled oscillator circuit shown in Fig. 15.1.1, represents the loss of each inductor. Each transistor is operating at a transconductance and has an output resistance . Find the oscillation frequency and explain why the circuit oscillates at this frequency. Also, derive an expression for the minimum value of needed to obtain sustained oscillations.
Figure 15.1.1

Figure 13.1.1
For the two-stage CMOS op amp shown in Fig. 13.1.1, all transistors have the same channel length , and . Transistors , and are matched; and are matched; and and are matched.
Parts (a) to (d) below deal with de bias calculations, and in these, assume the two input terminals are grounded and neglect the Early effect.
(a) Find the values of , and so that a dc voltage of appears at the gate of and dc current of flows in the drains of and .
(b) Find and that will result in each of and operating with an overdrive voltage of .
(c) Find and that will result in a dc voltage of at the gates of and .
(d) What de voltage appears at the gate of ? Find that will result in zero de current flowing through the output terminal of the amplifier.
(e) Find the input common-mode range.
(f) Find the allowable range of the output signal swing.
(g) Find the values of , and .
(h) Find the value of the differential gain of the first stage, .
(i) Recalling that the common-mode gain of the current-mirror-loaded differential amplifier is given by , where is the output resistance of , find , the commonmode gain, and the CMRR in .
(j) Find , and .
(k) Find the voltage gain of the second stage, .
(1) Find the overall differential voltage gain and the output resistance .
(m) If the feedback loop around the amplifier is closed by connecting the output terminal to the inverting input terminal, find the closedloop gain (between the non-inverting input terminal and the output) specified to four significant digits and determine the closed-loop output resistance .
(n) If, alternatively, the feedback loop around the op amp is closed by connecting the feedback network shown in Fig. 13.1.2, find the new values of and and the values of , the closed-loop gain , and the output resistance .
Figure 13.1.2


Figure 16.4.1
The transistors in the CMOS inverter in Fig. 16.4.1 have , and .
(a) What is the value of the gate threshold?
(b) For , what is the resistance between the output terminal and the supply? If a resistance is connected between the output terminal and ground, what will be?

In the current-mirror circuits in Fig. 13.3.1, all transistors are operating at the same current and have the same and the same . Identify each current-mirror (i.e., give its name) and give its output resistance in terms of , and . Also, give the minimum voltage each mirror requires to operate properly. Give in terms of and .

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