Exam 8: Operational Amplifier Circuits, Filters, Oscillators and CMOS Digital Logic Circuits

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     Figure 14.1.1 It is required to design a fifth-order Butterworth low-pass filter with a de gain of unity, a passband edge of  10^{4} \mathrm{rad} / \mathrm{s} , and a maximum deviation in the passband transmission of  3 \mathrm{~dB}  (i.e.,  \epsilon=1  ). (a) Find the transfer function  T(s)  and give  \omega_{0}  and  Q  of each of the two pairs of complex-conjugate poles. Also, specify the frequency of the real pole.  (b) Provide a complete circuit realization of the filter as a cascade of two second-order sections and a first-order section. For the second-order sections, use realizations based on the inductancesimulation circuit of Fig. 14.1.1. For the first-order section, use an op amp-RC circuit. Design so that all capacitors are equal to  10 \mathrm{nF}  and as many of the resistors as possible are equal. Give the complete circuit and specify the values of all resistors.  (c) What is the attenuation achieved at the stopband edge,  2 \times 10^{4} \mathrm{rad} / \mathrm{s}  ? Figure 14.1.1 It is required to design a fifth-order Butterworth low-pass filter with a de gain of unity, a passband edge of 104rad/s10^{4} \mathrm{rad} / \mathrm{s} , and a maximum deviation in the passband transmission of 3 dB3 \mathrm{~dB} (i.e., ϵ=1\epsilon=1 ). (a) Find the transfer function T(s)T(s) and give ω0\omega_{0} and QQ of each of the two pairs of complex-conjugate poles. Also, specify the frequency of the real pole. (b) Provide a complete circuit realization of the filter as a cascade of two second-order sections and a first-order section. For the second-order sections, use realizations based on the inductancesimulation circuit of Fig. 14.1.1. For the first-order section, use an op amp-RC circuit. Design so that all capacitors are equal to 10nF10 \mathrm{nF} and as many of the resistors as possible are equal. Give the complete circuit and specify the values of all resistors. (c) What is the attenuation achieved at the stopband edge, 2×104rad/s2 \times 10^{4} \mathrm{rad} / \mathrm{s} ?

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(a)
 (a)      Figure 14.1.2 Figure 14.1.2 shows the  s -plane locations of the poles. Here,  \begin{aligned} \omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\ \epsilon & \equiv \text { passband ripple factor }=1 \end{aligned}  The pair of complex-conjugate poles  p_{1}  and  p_{1}^{*}  have  \omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  \begin{aligned} \frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\ \Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618 \end{aligned}  The pair of complex-conjugate poles  p_{2}  and  p_{2}^{*}  have  \omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618  The real pole  p_{3}  has a frequency  \omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  Thus, the transfer function of the fifth-order lowpass filter is  T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}  where the numerator was found by enforcing the condition  T(0)=1   (b) Refer to Figure 14.1.3       Figure 14.1.3 Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,  \begin{aligned} C & =10 \mathrm{nF} \\ \omega_{0} & =10^{4}=\frac{1}{C R} \\ R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\ & =10 \mathrm{k} \Omega \end{aligned}  For the circuit realizing  \left(p_{1}, p_{1}^{*}\right) ,  Q R=1.618 \times 10=16.18 \mathrm{k} \Omega  For the circuit realizing  \left(p_{2}, p_{2}^{*}\right) ,  Q R=0.618 \times 10=6.18 \mathrm{k} \Omega  Each circuit has a unity de gain.      Figure 14.1.4 Figure 14.1.4 shows the circuit for realizing the real-axis pole,  p_{3} . Here  C=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega  The feedback resistance is selected equal to  R  so as to obtain a unity de gain. Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5       (c)  \begin{aligned} |T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\ A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB} \end{aligned}  where  \omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5  At  \omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,  \begin{aligned} A & =10 \log \left(1+2^{10}\right) \\ & =30.1 \mathrm{~dB} \end{aligned}       Figure 14.1.6

Figure 14.1.2
Figure 14.1.2 shows the ss -plane locations of the poles. Here,
ωp frequency of the passband edge =104rad/sϵ passband ripple factor =1\begin{aligned}\omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\\epsilon & \equiv \text { passband ripple factor }=1\end{aligned}
The pair of complex-conjugate poles p1p_{1} and p1p_{1}^{*} have
ω01=ωp=104rad/s\omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}
and
ω012Q1=ω01cos72Q1=12cos72=1.618\begin{aligned}\frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\\Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618\end{aligned}
The pair of complex-conjugate poles p2p_{2} and p2p_{2}^{*} have
ω02=ωp=104rad/s\omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}
and
Q2=12cos36=0.618Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618
The real pole p3p_{3} has a frequency
ω03=ωp=104rad/s\omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}
Thus, the transfer function of the fifth-order lowpass filter is
T(s)=1020(s+104)(s2+s1041.618+108)(s2+s1040.618+108)T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}
where the numerator was found by enforcing the condition T(0)=1T(0)=1

(b) Refer to Figure 14.1.3
 (a)      Figure 14.1.2 Figure 14.1.2 shows the  s -plane locations of the poles. Here,  \begin{aligned} \omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\ \epsilon & \equiv \text { passband ripple factor }=1 \end{aligned}  The pair of complex-conjugate poles  p_{1}  and  p_{1}^{*}  have  \omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  \begin{aligned} \frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\ \Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618 \end{aligned}  The pair of complex-conjugate poles  p_{2}  and  p_{2}^{*}  have  \omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618  The real pole  p_{3}  has a frequency  \omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  Thus, the transfer function of the fifth-order lowpass filter is  T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}  where the numerator was found by enforcing the condition  T(0)=1   (b) Refer to Figure 14.1.3       Figure 14.1.3 Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,  \begin{aligned} C & =10 \mathrm{nF} \\ \omega_{0} & =10^{4}=\frac{1}{C R} \\ R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\ & =10 \mathrm{k} \Omega \end{aligned}  For the circuit realizing  \left(p_{1}, p_{1}^{*}\right) ,  Q R=1.618 \times 10=16.18 \mathrm{k} \Omega  For the circuit realizing  \left(p_{2}, p_{2}^{*}\right) ,  Q R=0.618 \times 10=6.18 \mathrm{k} \Omega  Each circuit has a unity de gain.      Figure 14.1.4 Figure 14.1.4 shows the circuit for realizing the real-axis pole,  p_{3} . Here  C=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega  The feedback resistance is selected equal to  R  so as to obtain a unity de gain. Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5       (c)  \begin{aligned} |T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\ A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB} \end{aligned}  where  \omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5  At  \omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,  \begin{aligned} A & =10 \log \left(1+2^{10}\right) \\ & =30.1 \mathrm{~dB} \end{aligned}       Figure 14.1.6

Figure 14.1.3
Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,
C=10nFω0=104=1CRR=1ω0C=1104×10×109=10kΩ\begin{aligned}C & =10 \mathrm{nF} \\\omega_{0} & =10^{4}=\frac{1}{C R} \\R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\& =10 \mathrm{k} \Omega\end{aligned}
For the circuit realizing (p1,p1)\left(p_{1}, p_{1}^{*}\right) ,
QR=1.618×10=16.18kΩQ R=1.618 \times 10=16.18 \mathrm{k} \Omega
For the circuit realizing (p2,p2)\left(p_{2}, p_{2}^{*}\right) ,
QR=0.618×10=6.18kΩQ R=0.618 \times 10=6.18 \mathrm{k} \Omega
Each circuit has a unity de gain.
 (a)      Figure 14.1.2 Figure 14.1.2 shows the  s -plane locations of the poles. Here,  \begin{aligned} \omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\ \epsilon & \equiv \text { passband ripple factor }=1 \end{aligned}  The pair of complex-conjugate poles  p_{1}  and  p_{1}^{*}  have  \omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  \begin{aligned} \frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\ \Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618 \end{aligned}  The pair of complex-conjugate poles  p_{2}  and  p_{2}^{*}  have  \omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618  The real pole  p_{3}  has a frequency  \omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  Thus, the transfer function of the fifth-order lowpass filter is  T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}  where the numerator was found by enforcing the condition  T(0)=1   (b) Refer to Figure 14.1.3       Figure 14.1.3 Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,  \begin{aligned} C & =10 \mathrm{nF} \\ \omega_{0} & =10^{4}=\frac{1}{C R} \\ R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\ & =10 \mathrm{k} \Omega \end{aligned}  For the circuit realizing  \left(p_{1}, p_{1}^{*}\right) ,  Q R=1.618 \times 10=16.18 \mathrm{k} \Omega  For the circuit realizing  \left(p_{2}, p_{2}^{*}\right) ,  Q R=0.618 \times 10=6.18 \mathrm{k} \Omega  Each circuit has a unity de gain.      Figure 14.1.4 Figure 14.1.4 shows the circuit for realizing the real-axis pole,  p_{3} . Here  C=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega  The feedback resistance is selected equal to  R  so as to obtain a unity de gain. Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5       (c)  \begin{aligned} |T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\ A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB} \end{aligned}  where  \omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5  At  \omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,  \begin{aligned} A & =10 \log \left(1+2^{10}\right) \\ & =30.1 \mathrm{~dB} \end{aligned}       Figure 14.1.6

Figure 14.1.4
Figure 14.1.4 shows the circuit for realizing the real-axis pole, p3p_{3} . Here
C=10nF and R=1ω0C=10kΩC=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega
The feedback resistance is selected equal to RR so as to obtain a unity de gain.
Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5
 (a)      Figure 14.1.2 Figure 14.1.2 shows the  s -plane locations of the poles. Here,  \begin{aligned} \omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\ \epsilon & \equiv \text { passband ripple factor }=1 \end{aligned}  The pair of complex-conjugate poles  p_{1}  and  p_{1}^{*}  have  \omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  \begin{aligned} \frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\ \Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618 \end{aligned}  The pair of complex-conjugate poles  p_{2}  and  p_{2}^{*}  have  \omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618  The real pole  p_{3}  has a frequency  \omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  Thus, the transfer function of the fifth-order lowpass filter is  T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}  where the numerator was found by enforcing the condition  T(0)=1   (b) Refer to Figure 14.1.3       Figure 14.1.3 Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,  \begin{aligned} C & =10 \mathrm{nF} \\ \omega_{0} & =10^{4}=\frac{1}{C R} \\ R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\ & =10 \mathrm{k} \Omega \end{aligned}  For the circuit realizing  \left(p_{1}, p_{1}^{*}\right) ,  Q R=1.618 \times 10=16.18 \mathrm{k} \Omega  For the circuit realizing  \left(p_{2}, p_{2}^{*}\right) ,  Q R=0.618 \times 10=6.18 \mathrm{k} \Omega  Each circuit has a unity de gain.      Figure 14.1.4 Figure 14.1.4 shows the circuit for realizing the real-axis pole,  p_{3} . Here  C=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega  The feedback resistance is selected equal to  R  so as to obtain a unity de gain. Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5       (c)  \begin{aligned} |T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\ A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB} \end{aligned}  where  \omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5  At  \omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,  \begin{aligned} A & =10 \log \left(1+2^{10}\right) \\ & =30.1 \mathrm{~dB} \end{aligned}       Figure 14.1.6

(c)
T=11+(ω/ωp)2NA=10log[1+(ω/ωp)2N],dB\begin{aligned}|T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB}\end{aligned}
where
ωp=104rad/s and N=5\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5
At ω=ωS=2×104rad/s\omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,
A=10log(1+210)=30.1 dB\begin{aligned}A & =10 \log \left(1+2^{10}\right) \\& =30.1 \mathrm{~dB}\end{aligned}
 (a)      Figure 14.1.2 Figure 14.1.2 shows the  s -plane locations of the poles. Here,  \begin{aligned} \omega_{p} & \equiv \text { frequency of the passband edge }=10^{4} \mathrm{rad} / \mathrm{s} \\ \epsilon & \equiv \text { passband ripple factor }=1 \end{aligned}  The pair of complex-conjugate poles  p_{1}  and  p_{1}^{*}  have  \omega_{01}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  \begin{aligned} \frac{\omega_{01}}{2 Q_{1}} & =\omega_{01} \cos 72^{\circ} \\ \Rightarrow Q_{1} & =\frac{1}{2 \cos 72^{\circ}}=1.618 \end{aligned}  The pair of complex-conjugate poles  p_{2}  and  p_{2}^{*}  have  \omega_{02}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  and  Q_{2}=\frac{1}{2 \cos 36^{\circ}}=0.618  The real pole  p_{3}  has a frequency  \omega_{03}=\omega_{p}=10^{4} \mathrm{rad} / \mathrm{s}  Thus, the transfer function of the fifth-order lowpass filter is  T(s)=\frac{10^{20}}{\left(s+10^{4}\right)\left(s^{2}+s \frac{10^{4}}{1.618}+10^{8}\right)\left(s^{2}+s \frac{10^{4}}{0.618}+10^{8}\right)}  where the numerator was found by enforcing the condition  T(0)=1   (b) Refer to Figure 14.1.3       Figure 14.1.3 Each of the pair of complex-conjugate poles will be realized utilizing the low-pass circuit shown in Fig. 14.1.3. Here,  \begin{aligned} C & =10 \mathrm{nF} \\ \omega_{0} & =10^{4}=\frac{1}{C R} \\ R & =\frac{1}{\omega_{0} C}=\frac{1}{10^{4} \times 10 \times 10^{-9}} \\ & =10 \mathrm{k} \Omega \end{aligned}  For the circuit realizing  \left(p_{1}, p_{1}^{*}\right) ,  Q R=1.618 \times 10=16.18 \mathrm{k} \Omega  For the circuit realizing  \left(p_{2}, p_{2}^{*}\right) ,  Q R=0.618 \times 10=6.18 \mathrm{k} \Omega  Each circuit has a unity de gain.      Figure 14.1.4 Figure 14.1.4 shows the circuit for realizing the real-axis pole,  p_{3} . Here  C=10 \mathrm{nF} \quad \text { and } \quad R=\frac{1}{\omega_{0} C}=10 \mathrm{k} \Omega  The feedback resistance is selected equal to  R  so as to obtain a unity de gain. Placing the three sections in cascade provides the realization of the fifth-order Butterworth lowpass filter. The resulting circuit is shown in Fig. 14.1.5       (c)  \begin{aligned} |T| & =\frac{1}{\sqrt{1+\left(\omega / \omega_{p}\right)^{2 N}}} \\ A & =10 \log \left[1+\left(\omega / \omega_{p}\right)^{2 N}\right], \mathrm{dB} \end{aligned}  where  \omega_{p}=10^{4} \mathrm{rad} / \mathrm{s} \quad \text { and } \quad N=5  At  \omega=\omega_{S}=2 \times 10^{4} \mathrm{rad} / \mathrm{s} ,  \begin{aligned} A & =10 \log \left(1+2^{10}\right) \\ & =30.1 \mathrm{~dB} \end{aligned}       Figure 14.1.6

Figure 14.1.6

     Figure 16.3.1 The CMOS inverter shown in Fig. 16.3.1 is fabricated in a  0.18-\mu \mathrm{m}  technology having  \left|V_{t}\right|=0.4 \mathrm{~V} ,  k_{n}^{\prime}=0.4 \mathrm{~mA} / \mathrm{V}^{2} , and  \mu_{p}=\frac{1}{3} \mu_{n} . (a) Find  W_{p}  to obtain matched transistors. (b) For  v_{I}=1.8 \mathrm{~V} , find the maximum load current that the inverter can sink while  v_{O}  is not exceeding  0.1 \mathrm{~V} . Figure 16.3.1 The CMOS inverter shown in Fig. 16.3.1 is fabricated in a 0.18μm0.18-\mu \mathrm{m} technology having Vt=0.4 V\left|V_{t}\right|=0.4 \mathrm{~V} , kn=0.4 mA/V2k_{n}^{\prime}=0.4 \mathrm{~mA} / \mathrm{V}^{2} , and μp=13μn\mu_{p}=\frac{1}{3} \mu_{n} . (a) Find WpW_{p} to obtain matched transistors. (b) For vI=1.8 Vv_{I}=1.8 \mathrm{~V} , find the maximum load current that the inverter can sink while vOv_{O} is not exceeding 0.1 V0.1 \mathrm{~V} .

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    (a) For matching,  \begin{aligned} k_{n} & =k_{p} \\ \mu_{n} C_{o x}\left(\frac{W}{L}\right)_{N} & =\mu_{p} C_{o x}\left(\frac{W}{L}\right)_{P} \\ \mu_{n} \times \frac{0.27}{0.18} & =\frac{1}{3} \mu_{n} \times \frac{W_{p}}{0.18} \\ \Rightarrow W_{p} & =3 \times 0.27=0.81 \mu \mathrm{m} \end{aligned}   (b) For  v_{I}=1.8 \mathrm{~V}, Q_{N}  will be operating in the triode region:  i_{D N}=k_{n}\left[\left(v_{G S}-V_{t n}\right) v_{D S}-\frac{1}{2} v_{D S}^{2}\right]  For  v_{O}=0.1 \mathrm{~V} ,  \begin{aligned} i_{D N} & =0.4 \times \frac{0.27}{0.18}\left[(1.8-0.4) \times 0.1-\frac{1}{2} \times 0.1^{2}\right] \\ & =0.081 \mathrm{~mA} \\ & =81 \mu \mathrm{A} \end{aligned}
(a) For matching,
kn=kpμnCox(WL)N=μpCox(WL)Pμn×0.270.18=13μn×Wp0.18Wp=3×0.27=0.81μm\begin{aligned}k_{n} & =k_{p} \\\mu_{n} C_{o x}\left(\frac{W}{L}\right)_{N} & =\mu_{p} C_{o x}\left(\frac{W}{L}\right)_{P} \\\mu_{n} \times \frac{0.27}{0.18} & =\frac{1}{3} \mu_{n} \times \frac{W_{p}}{0.18} \\\Rightarrow W_{p} & =3 \times 0.27=0.81 \mu \mathrm{m}\end{aligned}

(b) For vI=1.8 V,QNv_{I}=1.8 \mathrm{~V}, Q_{N} will be operating in the triode region:
iDN=kn[(vGSVtn)vDS12vDS2]i_{D N}=k_{n}\left[\left(v_{G S}-V_{t n}\right) v_{D S}-\frac{1}{2} v_{D S}^{2}\right]
For vO=0.1 Vv_{O}=0.1 \mathrm{~V} ,
iDN=0.4×0.270.18[(1.80.4)×0.112×0.12]=0.081 mA=81μA\begin{aligned}i_{D N} & =0.4 \times \frac{0.27}{0.18}\left[(1.8-0.4) \times 0.1-\frac{1}{2} \times 0.1^{2}\right] \\& =0.081 \mathrm{~mA} \\& =81 \mu \mathrm{A}\end{aligned}

     The CMOS inverter shown in Fig. 16.2.1 has  V_{D D}=1.8 \mathrm{~V}  and is fabricated in a  0.18-\mu \mathrm{m}  process for which  \mu_{n}=4 \mu_{p}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2} , and  V_{t n}=-V_{t p}=0.4 \mathrm{~V} . For this problem, neglect the Early effect. Both  Q_{N}  and  Q_{P}  use the minimum channel length allowed. For  Q_{N}, W / L=1.5 . (a) Find the dimensions that  Q_{P}  must have in order for the inverter switching to occur at  v_{I}=0.9 \mathrm{~V} . (b) What are the noise margins of the inverter? (c) What current flows in  Q_{N}  and  Q_{P}  at the switching point? (d) For  v_{I}=1.8 \mathrm{~V} , what is the maximum current that  Q_{N}  can sink while  v_{O}  is limited to  0.4 \mathrm{~V}  ? The CMOS inverter shown in Fig. 16.2.1 has VDD=1.8 VV_{D D}=1.8 \mathrm{~V} and is fabricated in a 0.18μm0.18-\mu \mathrm{m} process for which μn=4μp,μnCox=400μA/V2\mu_{n}=4 \mu_{p}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2} , and Vtn=Vtp=0.4 VV_{t n}=-V_{t p}=0.4 \mathrm{~V} . For this problem, neglect the Early effect. Both QNQ_{N} and QPQ_{P} use the minimum channel length allowed. For QN,W/L=1.5Q_{N}, W / L=1.5 . (a) Find the dimensions that QPQ_{P} must have in order for the inverter switching to occur at vI=0.9 Vv_{I}=0.9 \mathrm{~V} . (b) What are the noise margins of the inverter? (c) What current flows in QNQ_{N} and QPQ_{P} at the switching point? (d) For vI=1.8 Vv_{I}=1.8 \mathrm{~V} , what is the maximum current that QNQ_{N} can sink while vOv_{O} is limited to 0.4 V0.4 \mathrm{~V} ?

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     Figure 16.2.1 (a) For the inverter switching to occur at  0.9 \mathrm{~V} , which is  V_{D D} / 2, Q_{N}  and  Q_{P}  must be matched:  \begin{aligned} k_{n} & =k_{p} \\ \mu_{n} C_{O x}\left(\frac{W}{L}\right)_{N} & =\mu_{p} C_{O x}\left(\frac{W}{L}\right)_{P} \end{aligned}  Thus,  \frac{(W / P)_{P}}{(W / L)_{N}}=\frac{\mu_{n}}{\mu_{p}}=4  Since  L_{N}=L_{P}=0.18 \mu \mathrm{m}  and  \begin{aligned} \left(\frac{W}{L}\right)_{N} & =1.5 \\ \Rightarrow W_{N} & =1.5 \times 0.18=0.27 \mu \mathrm{m} \\ W_{P} & =4 W_{N}=4 \times 0.27=1.08 \mu \mathrm{m} \end{aligned}  we obtain  \left(\frac{W}{L}\right)_{P}=\frac{1.08 \mu \mathrm{m}}{0.18 \mu \mathrm{m}}  (b)  \begin{aligned} V_{O H} & =V_{D D}=1.8 \mathrm{~V} \\ V_{O L} & =0 \mathrm{~V} \\ V_{I L} & =\frac{1}{8}\left(3 V_{D D}+2 V_{t}\right) \\ & =\frac{1}{8}(3 \times 1.8+2 \times 0.4) \\ & =0.775 \mathrm{~V} \\ N M_{L} & =V_{I L}-V_{O L}=0.775-0=0.775 \mathrm{~V} \\ N M_{H} & =N M_{L}=0.775 \mathrm{~V} \end{aligned}  (c) At the switching point,  Q_{N}  and  Q_{P}  operate in saturation:  \begin{aligned} I_{D} & =\frac{1}{2} \mu_{n} C_{o x}\left(\frac{W}{L}\right)_{N}\left(\frac{V_{D D}}{2}-V_{t}\right)^{2} \\ & =\frac{1}{2} \times 0.4 \times 1.5(0.9-0.4)^{2} \\ & =0.075 \mathrm{~mA}=75 \mu \mathrm{A} \end{aligned}  (d) For  v_{I}=1.8 \mathrm{~V}, Q_{N}  is operating in the triode region:  i_{D N}=k_{n}\left[\left(v_{G S}-V_{t n}\right) v_{D S}-\frac{1}{2} v_{D S}^{2}\right]  For  v_{G S}=1.8 \mathrm{~V}  and  v_{D S}=0.4 \mathrm{~V} ,  \begin{aligned} i_{D N} & =0.4 \times 1.5\left[(1.8-0.4) 0.4-\frac{1}{2} \times 0.4^{2}\right] \\ & =0.288 \mathrm{~mA} \end{aligned}

Figure 16.2.1
(a) For the inverter switching to occur at 0.9 V0.9 \mathrm{~V} , which is VDD/2,QNV_{D D} / 2, Q_{N} and QPQ_{P} must be matched:
kn=kpμnCOx(WL)N=μpCOx(WL)P\begin{aligned}k_{n} & =k_{p} \\\mu_{n} C_{O x}\left(\frac{W}{L}\right)_{N} & =\mu_{p} C_{O x}\left(\frac{W}{L}\right)_{P}\end{aligned}
Thus,
(W/P)P(W/L)N=μnμp=4\frac{(W / P)_{P}}{(W / L)_{N}}=\frac{\mu_{n}}{\mu_{p}}=4
Since LN=LP=0.18μmL_{N}=L_{P}=0.18 \mu \mathrm{m} and
(WL)N=1.5WN=1.5×0.18=0.27μmWP=4WN=4×0.27=1.08μm\begin{aligned}\left(\frac{W}{L}\right)_{N} & =1.5 \\\Rightarrow W_{N} & =1.5 \times 0.18=0.27 \mu \mathrm{m} \\W_{P} & =4 W_{N}=4 \times 0.27=1.08 \mu \mathrm{m}\end{aligned}
we obtain
(WL)P=1.08μm0.18μm\left(\frac{W}{L}\right)_{P}=\frac{1.08 \mu \mathrm{m}}{0.18 \mu \mathrm{m}}
(b)
VOH=VDD=1.8 VVOL=0 VVIL=18(3VDD+2Vt)=18(3×1.8+2×0.4)=0.775 VNML=VILVOL=0.7750=0.775 VNMH=NML=0.775 V\begin{aligned}V_{O H} & =V_{D D}=1.8 \mathrm{~V} \\V_{O L} & =0 \mathrm{~V} \\V_{I L} & =\frac{1}{8}\left(3 V_{D D}+2 V_{t}\right) \\& =\frac{1}{8}(3 \times 1.8+2 \times 0.4) \\& =0.775 \mathrm{~V} \\N M_{L} & =V_{I L}-V_{O L}=0.775-0=0.775 \mathrm{~V} \\N M_{H} & =N M_{L}=0.775 \mathrm{~V}\end{aligned}
(c) At the switching point, QNQ_{N} and QPQ_{P} operate in saturation:
ID=12μnCox(WL)N(VDD2Vt)2=12×0.4×1.5(0.90.4)2=0.075 mA=75μA\begin{aligned}I_{D} & =\frac{1}{2} \mu_{n} C_{o x}\left(\frac{W}{L}\right)_{N}\left(\frac{V_{D D}}{2}-V_{t}\right)^{2} \\& =\frac{1}{2} \times 0.4 \times 1.5(0.9-0.4)^{2} \\& =0.075 \mathrm{~mA}=75 \mu \mathrm{A}\end{aligned}
(d) For vI=1.8 V,QNv_{I}=1.8 \mathrm{~V}, Q_{N} is operating in the triode region:
iDN=kn[(vGSVtn)vDS12vDS2]i_{D N}=k_{n}\left[\left(v_{G S}-V_{t n}\right) v_{D S}-\frac{1}{2} v_{D S}^{2}\right]
For vGS=1.8 Vv_{G S}=1.8 \mathrm{~V} and vDS=0.4 Vv_{D S}=0.4 \mathrm{~V} ,
iDN=0.4×1.5[(1.80.4)0.412×0.42]=0.288 mA\begin{aligned}i_{D N} & =0.4 \times 1.5\left[(1.8-0.4) 0.4-\frac{1}{2} \times 0.4^{2}\right] \\& =0.288 \mathrm{~mA}\end{aligned}

     Figure 16.1.1 (a) For the CMOS inverter in Fig. 16.1.1,  Q_{N}  and  Q_{P}  have  \left|V_{t}\right|=0.5 \mathrm{~V}  and  k_{n}=k_{p}=1 \mathrm{~mA} / \mathrm{V}^{2} . Sketch and clearly label the VTC  v_{O}  versus  v_{I}  and give values for the noise margins  N M_{L}  and  N M_{H} . What is the output resistance when  v_{O}=0 \mathrm{~V}  ? (b) Provide the CMOS realization of the logic function.  Y=\overline{A(B+C)+D} Figure 16.1.1 (a) For the CMOS inverter in Fig. 16.1.1, QNQ_{N} and QPQ_{P} have Vt=0.5 V\left|V_{t}\right|=0.5 \mathrm{~V} and kn=kp=1 mA/V2k_{n}=k_{p}=1 \mathrm{~mA} / \mathrm{V}^{2} . Sketch and clearly label the VTC vOv_{O} versus vIv_{I} and give values for the noise margins NMLN M_{L} and NMHN M_{H} . What is the output resistance when vO=0 Vv_{O}=0 \mathrm{~V} ? (b) Provide the CMOS realization of the logic function. Y=A(B+C)+DY=\overline{A(B+C)+D}

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     Figure 13.2.1 It is required to design the folded-cascode op amp shown in Fig. 13.2.1. Let  V_{D D}=V_{S S}=1 \mathrm{~V}  and  V_{t n}=-V_{t p}=0.4 \mathrm{~V} , and assume that for all transistors,  \left|V_{A}\right|=6 \mathrm{~V} . Design so that the power dissipated in the circuit (with no input signal applied) is  0.6 \mathrm{~mW} , and so that each of  Q_{1}  and  Q_{2}  is operating at a current four times that at which each of  Q_{3}  and  Q_{4}  is operating. Also, design so that all transistors operate at  \left|V_{O V}\right|=0.2 \mathrm{~V} . (a) Show that the current drawn from each of the two power supplies is  2 I_{B} , and hence find  I_{B}  and  I  that result in the circuit operating at its specified power dissipation. (b) Find the dc current at which each of  Q_{1}  to  Q_{11}  is operating. Present your results in a table. (c) Find the input common-mode range.  (d) Find the required values of  V_{\mathrm{BIAS} 1}, V_{\mathrm{BIAS} 2} , and  V_{\mathrm{BIAS} 3}  that result in the maximum allowable value of  v_{O}  to be as high as possible. (e) Find the allowable range of  v_{O} . (f) Find the overall transconductance  G_{m} . (g) Find the output resistance  R_{O} . (h) Find the low-frequency voltage gain. (i) If the amplifier at its output is modeled by a controlled current-source  G_{m} V_{i d}  (where  V_{i d}  is the differential input voltage) feeding the output resistance  R_{O}  and the total capacitance at the output node  C_{L} , find the value of  C_{L}  that results in the amplifier having a unity-gain bandwidth of  100 \mathrm{MHz} . Assume that the dominant pole is that formed at the output. Figure 13.2.1 It is required to design the folded-cascode op amp shown in Fig. 13.2.1. Let VDD=VSS=1 VV_{D D}=V_{S S}=1 \mathrm{~V} and Vtn=Vtp=0.4 VV_{t n}=-V_{t p}=0.4 \mathrm{~V} , and assume that for all transistors, VA=6 V\left|V_{A}\right|=6 \mathrm{~V} . Design so that the power dissipated in the circuit (with no input signal applied) is 0.6 mW0.6 \mathrm{~mW} , and so that each of Q1Q_{1} and Q2Q_{2} is operating at a current four times that at which each of Q3Q_{3} and Q4Q_{4} is operating. Also, design so that all transistors operate at VOV=0.2 V\left|V_{O V}\right|=0.2 \mathrm{~V} . (a) Show that the current drawn from each of the two power supplies is 2IB2 I_{B} , and hence find IBI_{B} and II that result in the circuit operating at its specified power dissipation. (b) Find the dc current at which each of Q1Q_{1} to Q11Q_{11} is operating. Present your results in a table. (c) Find the input common-mode range. (d) Find the required values of VBIAS1,VBIAS2V_{\mathrm{BIAS} 1}, V_{\mathrm{BIAS} 2} , and VBIAS3V_{\mathrm{BIAS} 3} that result in the maximum allowable value of vOv_{O} to be as high as possible. (e) Find the allowable range of vOv_{O} . (f) Find the overall transconductance GmG_{m} . (g) Find the output resistance ROR_{O} . (h) Find the low-frequency voltage gain. (i) If the amplifier at its output is modeled by a controlled current-source GmVidG_{m} V_{i d} (where VidV_{i d} is the differential input voltage) feeding the output resistance ROR_{O} and the total capacitance at the output node CLC_{L} , find the value of CLC_{L} that results in the amplifier having a unity-gain bandwidth of 100MHz100 \mathrm{MHz} . Assume that the dominant pole is that formed at the output.

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In the cross-coupled oscillator circuit shown in Fig. 15.1.1, RpR_{p} represents the loss of each inductor. Each transistor is operating at a transconductance gmg_{m} and has an output resistance ror_{o} . Find the oscillation frequency ω0\omega_{0} and explain why the circuit oscillates at this frequency. Also, derive an expression for the minimum value of gmg_{m} needed to obtain sustained oscillations.  In the cross-coupled oscillator circuit shown in Fig. 15.1.1,  R_{p}  represents the loss of each inductor. Each transistor is operating at a transconductance  g_{m}  and has an output resistance  r_{o} . Find the oscillation frequency  \omega_{0}  and explain why the circuit oscillates at this frequency. Also, derive an expression for the minimum value of  g_{m}  needed to obtain sustained oscillations.      Figure 15.1.1 Figure 15.1.1

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     Figure 13.1.1 For the two-stage CMOS op amp shown in Fig. 13.1.1, all transistors have the same channel length  L=0.8 \mu \mathrm{m}, V_{t n}=-V_{t p}=0.6 \mathrm{~V}, \mu_{n} C_{o x}=   2 \mu_{p} C_{o x}=200 \mu \mathrm{A} / \mathrm{V}^{2} , and  \left|V_{A}\right|=20 \mathrm{~V} . Transistors  Q_{5}, Q_{7} , and  Q_{8}  are matched;  Q_{1}  and  Q_{2}  are matched; and  Q_{3}  and  Q_{4}  are matched. Parts (a) to (d) below deal with de bias calculations, and in these, assume the two input terminals are grounded and neglect the Early effect. (a) Find the values of  R, W_{8}, W_{5} , and  W_{7}  so that a dc voltage of  -1.5 \mathrm{~V}  appears at the gate of  Q_{5}  and dc current of  50 \mu \mathrm{A}  flows in the drains of  Q_{1}  and  Q_{2} . (b) Find  W_{1}  and  W_{2}  that will result in each of  Q_{1}  and  Q_{2}  operating with an overdrive voltage of  0.2 \mathrm{~V} . (c) Find  W_{3}  and  W_{4}  that will result in a dc voltage of  +1.5 \mathrm{~V}  at the gates of  Q_{3}  and  Q_{4} . (d) What de voltage appears at the gate of  Q_{6}  ? Find  W_{6}  that will result in zero de current flowing through the output terminal of the amplifier.  (e) Find the input common-mode range. (f) Find the allowable range of the output signal swing. (g) Find the values of  g_{m 1}, g_{m 2}, r_{o 2} , and  r_{o 4} . (h) Find the value of the differential gain of the first stage,  A_{1}=v_{o 1} / v_{i d} . (i) Recalling that the common-mode gain of the current-mirror-loaded differential amplifier is given by  \left(-1 / 2 g_{m 3} R_{S S}\right) , where  R_{S S}  is the output resistance of  Q_{5} , find  g_{m 3}, R_{S S} , the commonmode gain, and the CMRR in  \mathrm{dB} . (j) Find  g_{m 6}, r_{o 6} , and  r_{o 7} . (k) Find the voltage gain of the second stage,  A_{2}=   v_{0} / v_{01} . (1) Find the overall differential voltage gain  v_{O} / v_{i d}  and the output resistance  R_{O} . (m) If the feedback loop around the amplifier is closed by connecting the output terminal to the inverting input terminal, find the closedloop gain  A_{f}  (between the non-inverting input terminal and the output) specified to four significant digits and determine the closed-loop output resistance  R_{o f} . (n) If, alternatively, the feedback loop around the op amp is closed by connecting the feedback network shown in Fig. 13.1.2, find the new values of  A  and  R_{O}  and the values of  \beta , the closed-loop gain  A_{f} , and the output resistance  R_{o f} .      Figure 13.1.2 Figure 13.1.1 For the two-stage CMOS op amp shown in Fig. 13.1.1, all transistors have the same channel length L=0.8μm,Vtn=Vtp=0.6 V,μnCox=L=0.8 \mu \mathrm{m}, V_{t n}=-V_{t p}=0.6 \mathrm{~V}, \mu_{n} C_{o x}= 2μpCox=200μA/V22 \mu_{p} C_{o x}=200 \mu \mathrm{A} / \mathrm{V}^{2} , and VA=20 V\left|V_{A}\right|=20 \mathrm{~V} . Transistors Q5,Q7Q_{5}, Q_{7} , and Q8Q_{8} are matched; Q1Q_{1} and Q2Q_{2} are matched; and Q3Q_{3} and Q4Q_{4} are matched. Parts (a) to (d) below deal with de bias calculations, and in these, assume the two input terminals are grounded and neglect the Early effect. (a) Find the values of R,W8,W5R, W_{8}, W_{5} , and W7W_{7} so that a dc voltage of 1.5 V-1.5 \mathrm{~V} appears at the gate of Q5Q_{5} and dc current of 50μA50 \mu \mathrm{A} flows in the drains of Q1Q_{1} and Q2Q_{2} . (b) Find W1W_{1} and W2W_{2} that will result in each of Q1Q_{1} and Q2Q_{2} operating with an overdrive voltage of 0.2 V0.2 \mathrm{~V} . (c) Find W3W_{3} and W4W_{4} that will result in a dc voltage of +1.5 V+1.5 \mathrm{~V} at the gates of Q3Q_{3} and Q4Q_{4} . (d) What de voltage appears at the gate of Q6Q_{6} ? Find W6W_{6} that will result in zero de current flowing through the output terminal of the amplifier. (e) Find the input common-mode range. (f) Find the allowable range of the output signal swing. (g) Find the values of gm1,gm2,ro2g_{m 1}, g_{m 2}, r_{o 2} , and ro4r_{o 4} . (h) Find the value of the differential gain of the first stage, A1=vo1/vidA_{1}=v_{o 1} / v_{i d} . (i) Recalling that the common-mode gain of the current-mirror-loaded differential amplifier is given by (1/2gm3RSS)\left(-1 / 2 g_{m 3} R_{S S}\right) , where RSSR_{S S} is the output resistance of Q5Q_{5} , find gm3,RSSg_{m 3}, R_{S S} , the commonmode gain, and the CMRR in dB\mathrm{dB} . (j) Find gm6,ro6g_{m 6}, r_{o 6} , and ro7r_{o 7} . (k) Find the voltage gain of the second stage, A2=A_{2}= v0/v01v_{0} / v_{01} . (1) Find the overall differential voltage gain vO/vidv_{O} / v_{i d} and the output resistance ROR_{O} . (m) If the feedback loop around the amplifier is closed by connecting the output terminal to the inverting input terminal, find the closedloop gain AfA_{f} (between the non-inverting input terminal and the output) specified to four significant digits and determine the closed-loop output resistance RofR_{o f} . (n) If, alternatively, the feedback loop around the op amp is closed by connecting the feedback network shown in Fig. 13.1.2, find the new values of AA and ROR_{O} and the values of β\beta , the closed-loop gain AfA_{f} , and the output resistance RofR_{o f} .      Figure 13.1.1 For the two-stage CMOS op amp shown in Fig. 13.1.1, all transistors have the same channel length  L=0.8 \mu \mathrm{m}, V_{t n}=-V_{t p}=0.6 \mathrm{~V}, \mu_{n} C_{o x}=   2 \mu_{p} C_{o x}=200 \mu \mathrm{A} / \mathrm{V}^{2} , and  \left|V_{A}\right|=20 \mathrm{~V} . Transistors  Q_{5}, Q_{7} , and  Q_{8}  are matched;  Q_{1}  and  Q_{2}  are matched; and  Q_{3}  and  Q_{4}  are matched. Parts (a) to (d) below deal with de bias calculations, and in these, assume the two input terminals are grounded and neglect the Early effect. (a) Find the values of  R, W_{8}, W_{5} , and  W_{7}  so that a dc voltage of  -1.5 \mathrm{~V}  appears at the gate of  Q_{5}  and dc current of  50 \mu \mathrm{A}  flows in the drains of  Q_{1}  and  Q_{2} . (b) Find  W_{1}  and  W_{2}  that will result in each of  Q_{1}  and  Q_{2}  operating with an overdrive voltage of  0.2 \mathrm{~V} . (c) Find  W_{3}  and  W_{4}  that will result in a dc voltage of  +1.5 \mathrm{~V}  at the gates of  Q_{3}  and  Q_{4} . (d) What de voltage appears at the gate of  Q_{6}  ? Find  W_{6}  that will result in zero de current flowing through the output terminal of the amplifier.  (e) Find the input common-mode range. (f) Find the allowable range of the output signal swing. (g) Find the values of  g_{m 1}, g_{m 2}, r_{o 2} , and  r_{o 4} . (h) Find the value of the differential gain of the first stage,  A_{1}=v_{o 1} / v_{i d} . (i) Recalling that the common-mode gain of the current-mirror-loaded differential amplifier is given by  \left(-1 / 2 g_{m 3} R_{S S}\right) , where  R_{S S}  is the output resistance of  Q_{5} , find  g_{m 3}, R_{S S} , the commonmode gain, and the CMRR in  \mathrm{dB} . (j) Find  g_{m 6}, r_{o 6} , and  r_{o 7} . (k) Find the voltage gain of the second stage,  A_{2}=   v_{0} / v_{01} . (1) Find the overall differential voltage gain  v_{O} / v_{i d}  and the output resistance  R_{O} . (m) If the feedback loop around the amplifier is closed by connecting the output terminal to the inverting input terminal, find the closedloop gain  A_{f}  (between the non-inverting input terminal and the output) specified to four significant digits and determine the closed-loop output resistance  R_{o f} . (n) If, alternatively, the feedback loop around the op amp is closed by connecting the feedback network shown in Fig. 13.1.2, find the new values of  A  and  R_{O}  and the values of  \beta , the closed-loop gain  A_{f} , and the output resistance  R_{o f} .      Figure 13.1.2 Figure 13.1.2

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     Figure 16.4.1 The transistors in the CMOS inverter in Fig. 16.4.1 have  k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|=   1 \mathrm{~V} , and  \lambda=0 . (a) What is the value of the gate threshold? (b) For  v_{I}=0 \mathrm{~V} , what is the resistance between the output terminal and the  V_{D D}  supply? If a resistance  R_{L}=1 \mathrm{k} \Omega  is connected between the output terminal and ground, what will  v_{O}  be? Figure 16.4.1 The transistors in the CMOS inverter in Fig. 16.4.1 have kn(W/L)n=kp(W/L)p=10 mA/V2,Vt=k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|= 1 V1 \mathrm{~V} , and λ=0\lambda=0 . (a) What is the value of the gate threshold? (b) For vI=0 Vv_{I}=0 \mathrm{~V} , what is the resistance between the output terminal and the VDDV_{D D} supply? If a resistance RL=1kΩR_{L}=1 \mathrm{k} \Omega is connected between the output terminal and ground, what will vOv_{O} be?

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     In the current-mirror circuits in Fig. 13.3.1, all transistors are operating at the same current and have the same  V_{O V}  and the same  V_{A} . Identify each current-mirror (i.e., give its name) and give its output resistance  R_{O}  in terms of  I_{\mathrm{REF}}, V_{O V} , and  V_{A} . Also, give the minimum voltage  V_{O}  each mirror requires to operate properly. Give  V_{O}  in terms of  V_{t}  and  V_{O V} . In the current-mirror circuits in Fig. 13.3.1, all transistors are operating at the same current and have the same VOVV_{O V} and the same VAV_{A} . Identify each current-mirror (i.e., give its name) and give its output resistance ROR_{O} in terms of IREF,VOVI_{\mathrm{REF}}, V_{O V} , and VAV_{A} . Also, give the minimum voltage VOV_{O} each mirror requires to operate properly. Give VOV_{O} in terms of VtV_{t} and VOVV_{O V} .

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