Question 1

In S-R flip-flop, if Q = 0 the output is said to be

Accepted Answer

A) set 
B) reset 
C) previous state 
D) current state 
A) set 
B) reset 
C) previous state 
D) current state

Question 2

A latch is an example of a

Accepted Answer

A) monostable multivibrator 
B) astable multivibrator 
C) bistable multivibrator 
D) 555 timer 
A) monostable multivibrator 
B) astable multivibrator 
C) bistable multivibrator 
D) 555 timer

Question 3

When both inputs of SR latches are high, the latch goes

Accepted Answer

A) unstable 
B) stable 
C) metastable 
D) bistable 
A) unstable 
B) stable 
C) metastable 
D) bistable

Question 4

The first step of analysis procedure of SR latch is to

Accepted Answer

A) label inputs 
B) label outputs 
C) label states 
D) label tables 
A) label inputs 
B) label outputs 
C) label states 
D) label tables

Question 5

The output of latches will remain in set/reset untill

Accepted Answer

A) the trigger pulse is given to change the state 
B) any pulse given to go into previous state 
C) they don't get any pulse more 
D) the pulse is edge-triggered 
A) the trigger pulse is given to change the state 
B) any pulse given to go into previous state 
C) they don't get any pulse more 
D) the pulse is edge-triggered

In S-R flip-flop, if Q = 0 the output is said to be

A latch is an example of a

When both inputs of SR latches are high, the latch goes

The first step of analysis procedure of SR latch is to

The output of latches will remain in set/reset untill

Digital Circuit Design and RTL Implementation

Understanding Diode-Transistor Logic DTL and Other Logic Families

CMOS, ECL, SCFL, Lvpecl, and TTL Logic Circuits

TTL Circuits, Karnaugh Maps, and Flip-Flops

Flip-Flops and Mosfets in IC Components

Flip-Flops, Adders, and Subtractors

Registers, Shift Registers, and Adders

Exploring Concepts and Applications of Memory and Counters in Digital Electronics

Counters and Shift Registers

Proms and Memory Addressing

Binary Arithmetic and Multiplexers/Demultiplexers

Flip-Flops, Shift Operators, and Finite State Machines Fsm in VHDL

Shift Registers, Packages, and Combinational Circuits in VHDL

Filters

Exam 5: Sequential Circuits and Logic Gat

In S-R flip-flop, if Q = 0 the output is said to be

A latch is an example of a

When both inputs of SR latches are high, the latch goes

The first step of analysis procedure of SR latch is to

The output of latches will remain in set/reset untill

Digital Circuit Design and RTL Implementation

Understanding Diode-Transistor Logic DTL and Other Logic Families

CMOS, ECL, SCFL, Lvpecl, and TTL Logic Circuits

TTL Circuits, Karnaugh Maps, and Flip-Flops

Flip-Flops and Mosfets in IC Components

Flip-Flops, Adders, and Subtractors

Registers, Shift Registers, and Adders

Exploring Concepts and Applications of Memory and Counters in Digital Electronics

Counters and Shift Registers

Proms and Memory Addressing

Binary Arithmetic and Multiplexers/Demultiplexers

Flip-Flops, Shift Operators, and Finite State Machines Fsm in VHDL

Shift Registers, Packages, and Combinational Circuits in VHDL

Filters