Question 1

What will happen if the input analog voltage (Va) is greater than a digital- ramp ADC's full- scale (Vax) value?

Accepted Answer

A)  The counter will count up to its maximum value causing Vax to reach its full- scale output. All operations will then cease until Vax decreases below Vax. 
B)  The comparator will detect that Va is larger than the Vax full- scale output and all operations will cease until Va decreases below Vax full- scale. 
C)  The counter will repetitively count up from zero to maximum producing a continuously repetitive staircase waveform at Vax. 
D)  The comparator will detect that Va is beyond the range of Vax and will keep the ADC's output at zero until Va is decreased below Vax full- scale. 
A)  The counter will count up to its maximum value causing Vax to reach its full- scale output. All operations will then cease until Vax decreases below Vax. 
B)  The comparator will detect that Va is larger than the Vax full- scale output and all operations will cease until Va decreases below Vax full- scale. 
C)  The counter will repetitively count up from zero to maximum producing a continuously repetitive staircase waveform at Vax. 
D)  The comparator will detect that Va is beyond the range of Vax and will keep the ADC's output at zero until Va is decreased below Vax full- scale.

Question 2

The most likely ADC architecture for the majority of complex data acquisition systems is:

Accepted Answer

A)  successive approximation. 
B)  pipelined. 
C)  sigma/delta. 
D)  none of the above. 
A)  successive approximation. 
B)  pipelined. 
C)  sigma/delta. 
D)  none of the above.

Question 3

A digital- ramp ADC has the shortest conversion time of all ADC packages.

Accepted Answer

A) True 
 B)False

Question 4

What type of ADCs are becoming popular since they require fewer port bits to input data and thereby reduce the cost of the interface with the rest of the data acquisition system?

Accepted Answer

The answer of What type of ADCs are becoming popular...

Question 5

The resolution of a DAC is always equal to the weight of the LSB and is also referred to as the 	.

Accepted Answer

The answer of The resolution of a DAC is always...

Question 6

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 mA. How many possible output current steps can this DAC produce?

Accepted Answer

A)  99910  
B)  409610  
C)  409510  
D)  100010 
A)  99910  
B)  409610  
C)  409510  
D)  100010

Question 7

The two basic methods to test a DAC's operation consist of:

Accepted Answer

A)  a basic IC chip test to determine if: (1) the Vcc and (2) ground inputs are functioning normally. 
B)  a static accuracy test and a staircase test. 
C)  an analog- to- digital conversion test to determine DAC accuracy and a digital- to- analog conversion test. 
D)  a drift test to determine if the DAC output falls within the specified ranges and a quadrature test. 
A)  a basic IC chip test to determine if: (1) the Vcc and (2) ground inputs are functioning normally. 
B)  a static accuracy test and a staircase test. 
C)  an analog- to- digital conversion test to determine DAC accuracy and a digital- to- analog conversion test. 
D)  a drift test to determine if the DAC output falls within the specified ranges and a quadrature test.

Question 8

Sample- and- hold circuits in ADCs are designed to:

Accepted Answer

A)  sample and hold the output of the binary counter during the conversion process. 
B)  stabilize the input analog signal during the conversion process. 
C)  sample- and- hold the DAC staircase waveform during the conversion process. 
D)  stabilize the comparator's threshold voltage (VT) during the conversion process. 
A)  sample and hold the output of the binary counter during the conversion process. 
B)  stabilize the input analog signal during the conversion process. 
C)  sample- and- hold the DAC staircase waveform during the conversion process. 
D)  stabilize the comparator's threshold voltage (VT) during the conversion process.

Question 9

Flash A/D converters depend on an input clock pulse to perform each conversion.

Accepted Answer

A) True 
 B)False

Question 10

The digital representation of the process variable is transmitted from the ADC to the digital computer.

Accepted Answer

A) True 
 B)False

Question 11

The 	of a DAC is the smallest change that can occur in the analog output as a result of a change in the digital input.

Accepted Answer

The answer of The 	of a DAC is the smallest...

Question 12

Many analog to digital conversions circuits require clock signals.

Accepted Answer

A) True 
 B)False

Question 13

Which of the following A/D converters is the highest- speed ADC available?

Accepted Answer

A)  Flash 
B)  Successive- approximation 
C)  Digital- ramp 
A)  Flash 
B)  Successive- approximation 
C)  Digital- ramp

Question 14

ADCs use no clock signal because there is no timing or sequencing required.

Accepted Answer

The answer of ADCs use no clock signal because there...

Question 15

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 ma. What is the resolution of the DAC?

Accepted Answer

A)  12 µA 
B)  50 µA 
C)  11 µA 
D)  49 µA 
A)  12 µA 
B)  50 µA 
C)  11 µA 
D)  49 µA

Question 16

The output voltage or current of a digital- to- analog converter is truly an analog signal.

Accepted Answer

A) True 
 B)False

Question 17

Signal aliasing results in:

Accepted Answer

A)  the sampled signal representing the original input signal. 
B)  the sampled signal having a frequency that is half the original input signal. 
C)  the sampled signal having a frequency that is twice the original input signal. 
D)  the sampled signal having a frequency that is equal to the difference between the sample frequency and the incoming signal frequency. 
A)  the sampled signal representing the original input signal. 
B)  the sampled signal having a frequency that is half the original input signal. 
C)  the sampled signal having a frequency that is twice the original input signal. 
D)  the sampled signal having a frequency that is equal to the difference between the sample frequency and the incoming signal frequency.

Question 18

The process of a computer generating a START pulse, examining EOC, and loading ADC data into memory is controlled by:

Accepted Answer

A)  the clock pulse input to the ADC. 
B)  the data acquisition program. 
C)  the magnitude of VAX. 
D)  the magnitude of VA. 
A)  the clock pulse input to the ADC. 
B)  the data acquisition program. 
C)  the magnitude of VAX. 
D)  the magnitude of VA.

Question 19

D/A converters output ideal voltages. The actual output will vary from the ideal output for several different reasons. Which of the following is NOT a factor in determining output voltage accuracy?

Accepted Answer

A)  The precision of the resistor used in the summing amplifier output 
B)  The number of logic input bits 
C)  The precision of the input voltage level 
D)  The precision of the resistors used in the summing amplifier input 
A)  The precision of the resistor used in the summing amplifier output 
B)  The number of logic input bits 
C)  The precision of the input voltage level 
D)  The precision of the resistors used in the summing amplifier input

Question 20

In data acquisition systems, a single analog- to- digital converter (ADC) may be shared by several analog sources.

Accepted Answer

A) True 
 B)False

What will happen if the input analog voltage (V_a)is greater than a digital- ramp ADC's full- scale (V_ax) value?

The most likely ADC architecture for the majority of complex data acquisition systems is:

A digital- ramp ADC has the shortest conversion time of all ADC packages.

What type of ADCs are becoming popular since they require fewer port bits to input data and thereby reduce the cost of the interface with the rest of the data acquisition system?

The resolution of a DAC is always equal to the weight of the LSB and is also referred to as the .

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 mA. How many possible output current steps can this DAC produce?

The two basic methods to test a DAC's operation consist of:

Sample- and- hold circuits in ADCs are designed to:

Flash A/D converters depend on an input clock pulse to perform each conversion.

The digital representation of the process variable is transmitted from the ADC to the digital computer.

The of a DAC is the smallest change that can occur in the analog output as a result of a change in the digital input.

Many analog to digital conversions circuits require clock signals.

Which of the following A/D converters is the highest- speed ADC available?

ADCs use no clock signal because there is no timing or sequencing required.

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 ma. What is the resolution of the DAC?

The output voltage or current of a digital- to- analog converter is truly an analog signal.

Signal aliasing results in:

The process of a computer generating a START pulse, examining EOC, and loading ADC data into memory is controlled by:

D/A converters output ideal voltages. The actual output will vary from the ideal output for several different reasons. Which of the following is NOT a factor in determining output voltage accuracy?

In data acquisition systems, a single analog- to- digital converter (ADC) may be shared by several analog sources.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 11: Interfacing With the Analog World

What will happen if the input analog voltage (Va) is greater than a digital- ramp ADC's full- scale (Vax) value?

The most likely ADC architecture for the majority of complex data acquisition systems is:

A digital- ramp ADC has the shortest conversion time of all ADC packages.

What type of ADCs are becoming popular since they require fewer port bits to input data and thereby reduce the cost of the interface with the rest of the data acquisition system?

The resolution of a DAC is always equal to the weight of the LSB and is also referred to as the .

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 mA. How many possible output current steps can this DAC produce?

The two basic methods to test a DAC's operation consist of:

Sample- and- hold circuits in ADCs are designed to:

Flash A/D converters depend on an input clock pulse to perform each conversion.

The digital representation of the process variable is transmitted from the ADC to the digital computer.

The of a DAC is the smallest change that can occur in the analog output as a result of a change in the digital input.

Many analog to digital conversions circuits require clock signals.

Which of the following A/D converters is the highest- speed ADC available?

ADCs use no clock signal because there is no timing or sequencing required.

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 ma. What is the resolution of the DAC?

The output voltage or current of a digital- to- analog converter is truly an analog signal.

Signal aliasing results in:

The process of a computer generating a START pulse, examining EOC, and loading ADC data into memory is controlled by:

D/A converters output ideal voltages. The actual output will vary from the ideal output for several different reasons. Which of the following is NOT a factor in determining output voltage accuracy?

In data acquisition systems, a single analog- to- digital converter (ADC) may be shared by several analog sources.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Memory Devices

Programmable Logic Device Architectures

Filters

What will happen if the input analog voltage (V_a)is greater than a digital- ramp ADC's full- scale (V_ax) value?