Exam 10: Programmable Logic

An FPGA (Field Programmable Gate Array) basically consists of an array of logic blocks with programmable row and column interconnecting channels surrounded by programmable I/O blocks.

A LUT can be programmed to perform logic functions.

A PAL16H8 has 16 active high output pins.

The GAL consists of a reprogrammable array of AND gates that connects to a fixed array of OR gates.

An OLMC is an _________.

A PAL has a programmable AND array and a programmable OR array.

When a PAL is programmed, small fuses are blown open to allow connections between the input pins and the AND array.

Why are the input variables to a PAL buffered?

When tri- state outputs are used in a GAL22V10, _________.

For a GAL22V10, if the output from one pin is internally fed back to the input of another OLMC then the propagation time of the second pin would _________.

A typical FPGA logic element contains a 2- input LUT.

The typical EECMOS cell in a GAL will retain its programmed state for 5 to 10 years.

One advantage of PLDs over fixed- function logic devices is that many more logic circuits can be packaged in a much smaller area.

The main difference between a GAL and a PAL is that the GAL is reprogrammable.

Which Boolean Expressions are implemented by a PAL?

Input pins on PALs are buffered to allow both polarities of the input signal to be available to the array.

There is a limit to the number of product terms that can be assigned to each PAL output pin.

All SPLD software and programmers (regardless of the manufacturer) utilize JEDEC files that conform to established standards.

The output logic macrocell in a GAL16V8 is _________.

A GAL16V8 has ________.