Question 1

‪  
-Refer to Figure 9- 11. The output of the counter is checked and found to be 50 kHz. Is the counter working correctly? If not, what could be wrong?

Accepted Answer

A)  The counter is defective; there is probably a bad connection on the CTEN terminal of CTR0. 
B)  The counter is defective; an open exists somewhere between TC of CTR0 and CTEN of CTR1. 
C)  The counter is working correctly. 
D)  The counter is not working correctly; the TC of CTR1 is probably shorted to ground. 
A)  The counter is defective; there is probably a bad connection on the CTEN terminal of CTR0. 
B)  The counter is defective; an open exists somewhere between TC of CTR0 and CTEN of CTR1. 
C)  The counter is working correctly. 
D)  The counter is not working correctly; the TC of CTR1 is probably shorted to ground. B

Question 2

A Moore state machine does not have a clock input.

Accepted Answer

A) True 
 B)False  False

Question 3

The dot extension .CLK is used to indicate that the register device is a clocked flip- flop.

Accepted Answer

A) True 
 B)False  True

Question 4

‪  
-Referring to the waveforms in Figure 9- 3, what is the decimal count at point 'X'?

Accepted Answer

A)  7 
B)  0110 
C)  4 
D)  11 
A)  7 
B)  0110 
C)  4 
D)  11

Question 5

‪  
-An oscilloscope indicates that the circuit in Figure 9- 1 has no Q1 output signal. All J- K inputs are HIGH, the CLK signal is present and Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?

Accepted Answer

A)  The Q0 output should be connected to the J input of FFl. 
B)  The input of FF1 may be shorted to ground. 
C)  The output of FF0 may be shorted to ground. 
D)  The problem could be caused by either B or C. 
A)  The Q0 output should be connected to the J input of FFl. 
B)  The input of FF1 may be shorted to ground. 
C)  The output of FF0 may be shorted to ground. 
D)  The problem could be caused by either B or C.

Question 6

Most sequential circuits contain a combinational logic section and a memory section.

Accepted Answer

A) True 
 B)False

Question 7

‪  
-Refer to Figure 9- 8. What value should 'X' represent in the state table?

Accepted Answer

A)  1 
B)  0 
A)  1 
B)  0

Question 8

‪  
-What is the modulus of the counter shown in Figure 9- 9?

Accepted Answer

A)  0.005 
B)  5000 
C)  19 
D)  200 
A)  0.005 
B)  5000 
C)  19 
D)  200

Question 9

Which of the following statements is true?

Accepted Answer

A)  Asynchronous events are controlled by a clock. 
B)  Synchronous events do not need a clock to control them. 
C)  Only asynchronous events need a control clock. 
D)  Asynchronous events occur independently of the circuit clock. 
A)  Asynchronous events are controlled by a clock. 
B)  Synchronous events do not need a clock to control them. 
C)  Only asynchronous events need a control clock. 
D)  Asynchronous events occur independently of the circuit clock.

Question 10

The output from a Mealy state machine depends on its internal state and on external inputs.

Accepted Answer

A) True 
 B)False

Question 11

‪  
-Which of the following statements is correct concerning Figure 9- 4?

Accepted Answer

A)  Both the ENP and ENT terminals must be HIGH in order for the counter to cycle on the leading edge of the CLK input. 
B)  Both the active- LOW CLR and LOAD inputs must be LOW in order for the counter to cycle. 
C)  When the CLK input goes HIGH, the data on the DATA INPUT terminals is passed through to the DATA OUTPUT terminals. 
D)  The active- HIGH ENT and ENP inputs must be HIGH, while the active- LOW CLR and LOAD inputs must be LOW in order for the counter to cycle. 
A)  Both the ENP and ENT terminals must be HIGH in order for the counter to cycle on the leading edge of the CLK input. 
B)  Both the active- LOW CLR and LOAD inputs must be LOW in order for the counter to cycle. 
C)  When the CLK input goes HIGH, the data on the DATA INPUT terminals is passed through to the DATA OUTPUT terminals. 
D)  The active- HIGH ENT and ENP inputs must be HIGH, while the active- LOW CLR and LOAD inputs must be LOW in order for the counter to cycle.

Question 12

‪  
-What value does 'Z' represent in Figure 9- 8?

Accepted Answer

A)  111 
B)  3 
C)  5 
D)  4 
A)  111 
B)  3 
C)  5 
D)  4

Question 13

Counters are generally decoded in order to determine their count state.

Accepted Answer

A) True 
 B)False

Question 14

‪  
-The table shown in Figure 9- 6 is called a ________	.

Accepted Answer

A)  sequential truth table 
B)  present state table 
C)  state diagram 
D)  next- state table 
A)  sequential truth table 
B)  present state table 
C)  state diagram 
D)  next- state table

Question 15

The term synchronous as applied to counter operations means that the counter is clocked so that each flip- flop in the counter is triggered at the same time.

Accepted Answer

A) True 
 B)False

Question 16

‪  
-Refer to Figure 9- 11. The TC output of CTR0 shorts to ground; what will be the output frequency at 'X'?

Accepted Answer

A)  50 kHz 
B)  0 Hz 
C)  500 kHz 
D)  5 kHz 
A)  50 kHz 
B)  0 Hz 
C)  500 kHz 
D)  5 kHz

Question 17

A state machine has a finite number of states that occur in random order.

Accepted Answer

A) True 
 B)False

Question 18

Which type of state machine has a clock input?

Accepted Answer

A)  Moore 
B)  State machines do not have clock inputs. 
C)  Mealy 
D)  Moore and Mealy 
A)  Moore 
B)  State machines do not have clock inputs. 
C)  Mealy 
D)  Moore and Mealy

Question 19

‪  
-The logic expression for the Karnaugh map in Figure 9- 7 is ________.

Accepted Answer

A)    
B)    
C)    
D)    
A)    
B)    
C)    
D)

Question 20

‪  
-One of the most common and least expensive crystals available is the 3.58 MHz crystal used in color television sets. What hex value would have to be loaded into the counter in Figure 9- 12 in order to use the 3.58 MHz crystal to derive the 60Hz reference signal for the clock?

Accepted Answer

A)  E912 
B)  63C0 
C)  16ED 
D)  E3C0 
A)  E912 
B)  63C0 
C)  16ED 
D)  E3C0

‪ -Refer to Figure 9- 11. The output of the counter is checked and found to be 50 kHz. Is the counter working correctly? If not, what could be wrong?

A Moore state machine does not have a clock input.

The dot extension .CLK is used to indicate that the register device is a clocked flip- flop.

‪ -Referring to the waveforms in Figure 9- 3, what is the decimal count at point 'X'?

‪ -An oscilloscope indicates that the circuit in Figure 9- 1 has no Q1 output signal. All J- K inputs are HIGH, the CLK signal is present and Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?

Most sequential circuits contain a combinational logic section and a memory section.

‪ -Refer to Figure 9- 8. What value should 'X' represent in the state table?

‪ -What is the modulus of the counter shown in Figure 9- 9?

Which of the following statements is true?

The output from a Mealy state machine depends on its internal state and on external inputs.

‪ -Which of the following statements is correct concerning Figure 9- 4?

‪ -What value does 'Z' represent in Figure 9- 8?

Counters are generally decoded in order to determine their count state.

‪ -The table shown in Figure 9- 6 is called a ________ .

The term synchronous as applied to counter operations means that the counter is clocked so that each flip- flop in the counter is triggered at the same time.

‪ -Refer to Figure 9- 11. The TC output of CTR0 shorts to ground; what will be the output frequency at 'X'?

A state machine has a finite number of states that occur in random order.

Which type of state machine has a clock input?

‪ -The logic expression for the Karnaugh map in Figure 9- 7 is ________.

‪ -One of the most common and least expensive crystals available is the 3.58 MHz crystal used in color television sets. What hex value would have to be loaded into the counter in Figure 9- 12 in order to use the 3.58 MHz crystal to derive the 60Hz reference signal for the clock?

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Latches, Flip-Flops, and Timers

Shift Registers

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters

Exam 9: Counters

‪ -Refer to Figure 9- 11. The output of the counter is checked and found to be 50 kHz. Is the counter working correctly? If not, what could be wrong?

A Moore state machine does not have a clock input.

The dot extension .CLK is used to indicate that the register device is a clocked flip- flop.

‪ -Referring to the waveforms in Figure 9- 3, what is the decimal count at point 'X'?

‪ -An oscilloscope indicates that the circuit in Figure 9- 1 has no Q1 output signal. All J- K inputs are HIGH, the CLK signal is present and Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?

Most sequential circuits contain a combinational logic section and a memory section.

‪ -Refer to Figure 9- 8. What value should 'X' represent in the state table?

‪ -What is the modulus of the counter shown in Figure 9- 9?

Which of the following statements is true?

The output from a Mealy state machine depends on its internal state and on external inputs.

‪ -Which of the following statements is correct concerning Figure 9- 4?

‪ -What value does 'Z' represent in Figure 9- 8?

Counters are generally decoded in order to determine their count state.

‪ -The table shown in Figure 9- 6 is called a ________ .

The term synchronous as applied to counter operations means that the counter is clocked so that each flip- flop in the counter is triggered at the same time.

‪ -Refer to Figure 9- 11. The TC output of CTR0 shorts to ground; what will be the output frequency at 'X'?

A state machine has a finite number of states that occur in random order.

Which type of state machine has a clock input?

‪ -The logic expression for the Karnaugh map in Figure 9- 7 is ________.

‪ -One of the most common and least expensive crystals available is the 3.58 MHz crystal used in color television sets. What hex value would have to be loaded into the counter in Figure 9- 12 in order to use the 3.58 MHz crystal to derive the 60Hz reference signal for the clock?

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Latches, Flip-Flops, and Timers

Shift Registers

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters