Exam 7: Latches, Flip-Flops, and Timers
Exam 1: Introductory Concepts75 Questions
Exam 2: Number Systems, Operations, and Codes49 Questions
Exam 3: Logic Gates56 Questions
Exam 4: Boolean Algebra and Logic Simplification46 Questions
Exam 5: Combinational Logic Analysis38 Questions
Exam 6: Functions of Combinational Logic46 Questions
Exam 7: Latches, Flip-Flops, and Timers38 Questions
Exam 8: Shift Registers40 Questions
Exam 9: Counters50 Questions
Exam 10: Programmable Logic30 Questions
Exam 11: Data Storage49 Questions
Exam 12: Signal Conversion and Processing46 Questions
Exam 13: Data Transmission99 Questions
Exam 14: Data Processing and Control127 Questions
Exam 15: Integrated Circuit Technologies40 Questions
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Which of the following is correct for a gated D latch?
Free
(Multiple Choice)
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Correct Answer:
C
The symbol for an edge- triggered flip- flop has a triangle on its clock input.
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(True/False)
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Correct Answer:
True
These waveforms are applied to a gated D latch, which is initially RESET. Which of the areas identified on the Q waveform is incorrect?


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(Multiple Choice)
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Correct Answer:
C
The asynchronous inputs to a flip- flop are normally labeled_____and________ , and are normally active_______inputs.
(Multiple Choice)
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A push- button switch is used to input data to a register. The output of the register is erratic. Which of the following could be the cause of the problem?
(Multiple Choice)
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The ON time of a 555 monostable multivibrator is determined by tw = 1.1RC.
(True/False)
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When both inputs of a J- K pulse- triggered FF are high, and the clock cycles, the output wil_________
(Multiple Choice)
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An active- HIGH input S- R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
(Multiple Choice)
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A diode can be added to the discharge path for a 555 astable multivibrator to obtain duty cycles that are less than 50%.
(True/False)
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What primary advantage does the J- K flip- flop have over the S- R flip- flop?
(Multiple Choice)
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What symbol is used to identify edge- triggered flip- flops?
(Multiple Choice)
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A positive edge- triggered J- K flip- flop is used to produce a two- phase clock. However, when the circuit is operated it produces erratic results. Close examination with an oscilloscope reveals the presence of glitches. What might be the source of these glitches?
(Multiple Choice)
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How is the invalid input state problem associated with the S- R flip- flop overcome?
(Multiple Choice)
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A J- K flip- flop is being used as a divide- by- 2 circuit when _________.
(Multiple Choice)
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A one- shot is a multivibrator that must be triggered to produce each output pulse.
(True/False)
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The J- K flip- flop toggles when both inputs are high during the transition of the clock signal.
(True/False)
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