Question 1

Which of the following is the most common use of flip- flops?

Accepted Answer

A)  Switch debouncing 
B)  Pulse steering circuits 
C)  Combinatorial logic arrays 
D)  Storage registers 
A)  Switch debouncing 
B)  Pulse steering circuits 
C)  Combinatorial logic arrays 
D)  Storage registers

Question 2

Which of the following can result from a slow input signal transition?

Accepted Answer

A)  Erratic triggering of flip- flops 
B)  Failure to produce an output signal 
C)  Oscillations may occur on the output of logic gates and inverters. 
D)  Both A and C 
E)  Both B and C 
A)  Erratic triggering of flip- flops 
B)  Failure to produce an output signal 
C)  Oscillations may occur on the output of logic gates and inverters. 
D)  Both A and C 
E)  Both B and C

Question 3

Flip- flops can be used as sequencing components.

Accepted Answer

A) True 
 B)False

Question 4

Mechanical switches are susceptible to_____, which can be eliminated by using a NAND gate latch.

Accepted Answer

Contact bo

Question 5

How many shift pulses would be required to serially shift the contents of one six- stage register to another?

Accepted Answer

A)  8 
B)  5 
C)  6 
D)  7 
A)  8 
B)  5 
C)  6 
D)  7

Question 6

You need to build a circuit to perform parallel data transfers from one set of registers to another. The interconnections between the registers must be held to a minimum. The best choice for the register FFs is the _____type.

Accepted Answer

A)  latch 
B)  "D" 
C)  "J- K" 
D)  "S- C" 
A)  latch 
B)  "D" 
C)  "J- K" 
D)  "S- C"

Question 7

Which statement best describes the operation of a NGT- triggered D flip- flop?

Accepted Answer

A)  The Q output is always identical to the D input. 
B)  The Q output is always identical to the CLK input if the D input is HIGH. 
C)  The Q output is always identical to the D input when CLK makes a PGT. 
D)  The logic level at the D input is transferred to Q on NGT of CLK. 
A)  The Q output is always identical to the D input. 
B)  The Q output is always identical to the CLK input if the D input is HIGH. 
C)  The Q output is always identical to the D input when CLK makes a PGT. 
D)  The logic level at the D input is transferred to Q on NGT of CLK.

Question 8

A clock makes a _____transition when it switches from a zero to a one.

Accepted Answer

The answer of A clock makes a _____transition when it...

Question 9

An_____input is activated by a signal transition rather than a logic level.

Accepted Answer

The answer of An_____input is activated by a signal transition...

Question 10

Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip- flop in a circuit application where they are NOT used?

Accepted Answer

A)  Connect the   and   inputs to a HIGH logic level. 
B)  Connect the   and   inputs to a LOW logic level. 
C)  Connect the   input to a HIGH logic level and the  to a LOW logic level. 
D)  Connect the  input to a LOW logic level and the   input to a HIGH logic level. 
A)  Connect the   and   inputs to a HIGH logic level. 
B)  Connect the   and   inputs to a LOW logic level. 
C)  Connect the   input to a HIGH logic level and the  to a LOW logic level. 
D)  Connect the  input to a LOW logic level and the   input to a HIGH logic level.

Question 11

In _____circuits, the outputs of logic circuits can change state independently of a clock (CLK) input.

Accepted Answer

The answer of In _____circuits, the outputs of logic circuits...

Question 12

Which of the following logic devices has only one stable state?

Accepted Answer

A)  Monostable multivibrator 
B)  Astable multivibrator 
C)  J- K flip- flop 
D)  S- C flip- flop 
A)  Monostable multivibrator 
B)  Astable multivibrator 
C)  J- K flip- flop 
D)  S- C flip- flop

Question 13

LPMs are found in the megafunction library of Altera's Quartus II software.

Accepted Answer

A) True 
 B)False

Question 14

What type of multivibrator has no stable state?

Accepted Answer

A)  Bistable 
B)  Astable 
C)  Monostable 
D)  Both A and C 
A)  Bistable 
B)  Astable 
C)  Monostable 
D)  Both A and C

Question 15

Three flip- flops are wired together as a binary counter and the input clock frequency is 600 Hz. What is the output frequency of the highest order Q output?

Accepted Answer

A)  50 Hz 
B)  120 Hz 
C)  100 Hz 
D)  60 Hz 
A)  50 Hz 
B)  120 Hz 
C)  100 Hz 
D)  60 Hz

Question 16

A(n)_____ 	input does not require a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

Accepted Answer

The answer of A(n)_____ 	input does not require a clock...

Question 17

The combination of Q = 1 and   = 0 defines the:

Accepted Answer

A)  flip- flop clear state. 
B)  flip- flop set state. 
C)  flip- flop reset state. 
D)  Both B and C 
A)  flip- flop clear state. 
B)  flip- flop set state. 
C)  flip- flop reset state. 
D)  Both B and C

Question 18

Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

Accepted Answer

A)  active LOW input NOR gates 
B)  active HIGH input NOR gates 
C)  active LOW input OR gates 
D)  active HIGH input AND gates 
A)  active LOW input NOR gates 
B)  active HIGH input NOR gates 
C)  active LOW input OR gates 
D)  active HIGH input AND gates

Question 19

A flip- flop is in the HIGH state when Q = 1.

Accepted Answer

A) True 
 B)False

Question 20

An open or "floating" input on a flip- flop may pick up enough noise to cause the device to change states.

Accepted Answer

A) True 
 B)False

Which of the following is the most common use of flip- flops?

Which of the following can result from a slow input signal transition?

Flip- flops can be used as sequencing components.

Mechanical switches are susceptible to_____, which can be eliminated by using a NAND gate latch.

How many shift pulses would be required to serially shift the contents of one six- stage register to another?

You need to build a circuit to perform parallel data transfers from one set of registers to another. The interconnections between the registers must be held to a minimum. The best choice for the register FFs is the _____type.

Which statement best describes the operation of a NGT- triggered D flip- flop?

A clock makes a _____transition when it switches from a zero to a one.

An_____input is activated by a signal transition rather than a logic level.

Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip- flop in a circuit application where they are NOT used?

In _____circuits, the outputs of logic circuits can change state independently of a clock (CLK) input.

Which of the following logic devices has only one stable state?

LPMs are found in the megafunction library of Altera's Quartus II software.

What type of multivibrator has no stable state?

Three flip- flops are wired together as a binary counter and the input clock frequency is 600 Hz. What is the output frequency of the highest order Q output?

A(n)_____ input does not require a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

The combination of Q = 1 and = 0 defines the:

Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

A flip- flop is in the HIGH state when Q = 1.

An open or "floating" input on a flip- flop may pick up enough noise to cause the device to change states.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 5: Flip-Flops and Related Devices

Which of the following is the most common use of flip- flops?

Which of the following can result from a slow input signal transition?

Flip- flops can be used as sequencing components.

Mechanical switches are susceptible to_____, which can be eliminated by using a NAND gate latch.

How many shift pulses would be required to serially shift the contents of one six- stage register to another?

You need to build a circuit to perform parallel data transfers from one set of registers to another. The interconnections between the registers must be held to a minimum. The best choice for the register FFs is the _____type.

Which statement best describes the operation of a NGT- triggered D flip- flop?

A clock makes a _____transition when it switches from a zero to a one.

An_____input is activated by a signal transition rather than a logic level.

Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip- flop in a circuit application where they are NOT used?

In _____circuits, the outputs of logic circuits can change state independently of a clock (CLK) input.

Which of the following logic devices has only one stable state?

LPMs are found in the megafunction library of Altera's Quartus II software.

What type of multivibrator has no stable state?

Three flip- flops are wired together as a binary counter and the input clock frequency is 600 Hz. What is the output frequency of the highest order Q output?

A(n)_____ input does not require a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

The combination of Q = 1 and = 0 defines the:

Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

A flip- flop is in the HIGH state when Q = 1.

An open or "floating" input on a flip- flop may pick up enough noise to cause the device to change states.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters