Question 1

A negative- edge- triggered J- K flip- flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?

Accepted Answer

A)  CLK = NGT, J = O, and K = 1 
B)  CLK = NGT, J = 1, and K = 0 
C)  CLK = PGT, J = 1, and K = 0 
D)  CLK = PGT, J = O, and K = 1 
A)  CLK = NGT, J = O, and K = 1 
B)  CLK = NGT, J = 1, and K = 0 
C)  CLK = PGT, J = 1, and K = 0 
D)  CLK = PGT, J = O, and K = 1

Question 2

Select the statement that best describes the operation of retriggerable and non- retriggerable one- shot multivibrators.

Accepted Answer

A)  A non- retriggerable one- shot may be retriggered in either its quasi- stable or stable state. 
B)  A retriggerable one- shot may be retriggered while in its quasi- stable state. 
C)  A non- retriggerable one- shot may be retriggered only while in its quasi- stable state. 
D)  A retriggerable one- shot must return to its stable state before it can be retriggered. 
A)  A non- retriggerable one- shot may be retriggered in either its quasi- stable or stable state. 
B)  A retriggerable one- shot may be retriggered while in its quasi- stable state. 
C)  A non- retriggerable one- shot may be retriggered only while in its quasi- stable state. 
D)  A retriggerable one- shot must return to its stable state before it can be retriggered.

Question 3

What is the output state of a MOD- 64 counter after 92 input pulses if the starting state is 000000?

Accepted Answer

A)  0111102  
B)  0101102  
C)  0111002  
D)  1001002 
A)  0111102  
B)  0101102  
C)  0111002  
D)  1001002

Question 4

A primary difference between a clocked J- K flip- flop and a clocked S- C flip- flop is the J- K's ability to:

Accepted Answer

A)  always reset to the CLEAR state when J = 1, K = 1, and a clock transition occurs. 
B)  remain in the CLEAR state when J = 1, K = 0, and a clock transition occurs. 
C)  toggle or change states when J = 1, K = 1, and a clock transition occurs. 
D)  always reset to the set state when J = 1, K = 1, and a clock transition occurs. 
A)  always reset to the CLEAR state when J = 1, K = 1, and a clock transition occurs. 
B)  remain in the CLEAR state when J = 1, K = 0, and a clock transition occurs. 
C)  toggle or change states when J = 1, K = 1, and a clock transition occurs. 
D)  always reset to the set state when J = 1, K = 1, and a clock transition occurs.

Question 5

Synchronous flip- flops require a clock input to change output states.

Accepted Answer

A) True 
 B)False

Question 6

Figure 5- 1   The clocked S- C flip- flop in Figure 5- 1 is synchronized by the CLK pulse when:

Accepted Answer

A)  the clock pulse transitions from LOW to HIGH. 
B)  the clock pulse transitions either HIGH- LOW or LOW- HIGH. 
C)  the clock pulse remains a constant HIGH. 
D)  the clock pulse remains a constant LOW. 
E)  the clock pulse transitions from HIGH to LOW. 
A)  the clock pulse transitions from LOW to HIGH. 
B)  the clock pulse transitions either HIGH- LOW or LOW- HIGH. 
C)  the clock pulse remains a constant HIGH. 
D)  the clock pulse remains a constant LOW. 
E)  the clock pulse transitions from HIGH to LOW.

Question 7

As a general rule for stable flip- flop triggering, the clock pulse rise and fall times must be:

Accepted Answer

A)  of no consequence as long as the levels are within the determinate range of values. 
B)  at a maximum value to enable the input control signals to stabilize. 
C)  very short. 
D)  very long. 
A)  of no consequence as long as the levels are within the determinate range of values. 
B)  at a maximum value to enable the input control signals to stabilize. 
C)  very short. 
D)  very long.

Question 8

The asynchronous transfer of data between J- K storage registers can easily be accomplished using the:

Accepted Answer

A)  PRESET and CLEAR inputs only. 
B)  Clock and the input J- K control signals. 
C)  Clock with the PRESET and CLEAR inputs. 
D)  J- K control signals only. 
A)  PRESET and CLEAR inputs only. 
B)  Clock and the input J- K control signals. 
C)  Clock with the PRESET and CLEAR inputs. 
D)  J- K control signals only.

Question 9

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

Accepted Answer

A)  the FF is level active and can only change states when the CLOCK = 1. 
B)  the FF is edge- triggered and can only change states when the clock goes 0 to 1. 
C)  the FF is an active LOW device and can only change states when the CLOCK = 0. 
D)  the FF is edge- triggered and can only change states when the clock goes from 1 to 0. 
A)  the FF is level active and can only change states when the CLOCK = 1. 
B)  the FF is edge- triggered and can only change states when the clock goes 0 to 1. 
C)  the FF is an active LOW device and can only change states when the CLOCK = 0. 
D)  the FF is edge- triggered and can only change states when the clock goes from 1 to 0.

Question 10

Select the statement that best describes the two possible output states of a flip- flop.

Accepted Answer

A)  The Q output is LOW and the  output is LOW. 
B)  The Q output is LOW and the   output is HIGH. 
C)  The Q output is HIGH and the   output is LOW. 
D)  The Q output is HIGH and the   output is HIGH. 
E)  Both B and C 
A)  The Q output is LOW and the  output is LOW. 
B)  The Q output is LOW and the   output is HIGH. 
C)  The Q output is HIGH and the   output is LOW. 
D)  The Q output is HIGH and the   output is HIGH. 
E)  Both B and C

Question 11

The preset and clear inputs to a J- K flip- flop are HIGH (1). Which of the following is TRUE?

Accepted Answer

A)  The Q output is in an ambiguous state. 
B)  The Q output is immediately set to 1. 
C)  The flip- flop is free to respond to its J, K, and clock inputs. 
D)  The Q output is immediately cleared. 
A)  The Q output is in an ambiguous state. 
B)  The Q output is immediately set to 1. 
C)  The flip- flop is free to respond to its J, K, and clock inputs. 
D)  The Q output is immediately cleared.

Question 12

The usual stable state for one- shot is: Q = 1, Q = 0.

Accepted Answer

A) True 
 B)False

Question 13

What type of multivibrator produces a continuous pulse train?

Accepted Answer

A)  Bistable 
B)  Astable 
C)  Monostable 
D)  all of the above 
A)  Bistable 
B)  Astable 
C)  Monostable 
D)  all of the above

Question 14

The three libraries in Altara's Quartus II development system software are named_____ ,_____ and_____ .

Accepted Answer

primitives

Question 15

Which of the following statements best describes an asynchronous digital system?

Accepted Answer

A)  It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change. 
B)  It is easy to design and troubleshoot because the output state is independent of the inputs. 
C)  It is difficult to design and troubleshoot because the output cannot change states unless a clock input is synchronized to the SET and CLEAR inputs. 
D)  It is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal. 
A)  It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change. 
B)  It is easy to design and troubleshoot because the output state is independent of the inputs. 
C)  It is difficult to design and troubleshoot because the output cannot change states unless a clock input is synchronized to the SET and CLEAR inputs. 
D)  It is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal.

Question 16

A flip- flop is always SET by the positive- going transition that occurs when power is first applied.

Accepted Answer

A) True 
 B)False

Question 17

Retriggerable one- shots tend to reduce the HIGH (quasi- stable) output time upon successive triggers.

Accepted Answer

A) True 
 B)False

Question 18

Flip- flops are integral to all electronic data transfer and memory systems.

Accepted Answer

A) True 
 B)False

Question 19

When operated in its_____mode, a FF changes states with each clock pulse.

Accepted Answer

The answer of When operated in its_____mode, a FF changes...

Question 20

A 1.5 MHZ clock signal is applied to an eight flip- flop binary counter. Which of the following indicates the proper MOD number, maximum number of counts, maximum count, and output frequency of the circuit?

Accepted Answer

A)  MOD 128, 128 counts, 127 maximum count, and 23,437.5 Hz 
B)  MOD 512, 512 counts, 511 maximum count, and 2,929.69 Hz 
C)  MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz 
D)  MOD 256, 256 counts, 255 maximum count, and 11,718.75 Hz 
A)  MOD 128, 128 counts, 127 maximum count, and 23,437.5 Hz 
B)  MOD 512, 512 counts, 511 maximum count, and 2,929.69 Hz 
C)  MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz 
D)  MOD 256, 256 counts, 255 maximum count, and 11,718.75 Hz

A negative- edge- triggered J- K flip- flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?

Select the statement that best describes the operation of retriggerable and non- retriggerable one- shot multivibrators.

What is the output state of a MOD- 64 counter after 92 input pulses if the starting state is 000000?

A primary difference between a clocked J- K flip- flop and a clocked S- C flip- flop is the J- K's ability to:

Synchronous flip- flops require a clock input to change output states.

Figure 5- 1 The clocked S- C flip- flop in Figure 5- 1 is synchronized by the CLK pulse when:

As a general rule for stable flip- flop triggering, the clock pulse rise and fall times must be:

The asynchronous transfer of data between J- K storage registers can easily be accomplished using the:

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

Select the statement that best describes the two possible output states of a flip- flop.

The preset and clear inputs to a J- K flip- flop are HIGH (1). Which of the following is TRUE?

The usual stable state for one- shot is: Q = 1, Q = 0.

What type of multivibrator produces a continuous pulse train?

The three libraries in Altara's Quartus II development system software are named___ ,_ and___ .

Which of the following statements best describes an asynchronous digital system?

A flip- flop is always SET by the positive- going transition that occurs when power is first applied.

Retriggerable one- shots tend to reduce the HIGH (quasi- stable) output time upon successive triggers.

Flip- flops are integral to all electronic data transfer and memory systems.

When operated in its_____mode, a FF changes states with each clock pulse.

A 1.5 MHZ clock signal is applied to an eight flip- flop binary counter. Which of the following indicates the proper MOD number, maximum number of counts, maximum count, and output frequency of the circuit?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 5: Flip-Flops and Related Devices

A negative- edge- triggered J- K flip- flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?

Select the statement that best describes the operation of retriggerable and non- retriggerable one- shot multivibrators.

What is the output state of a MOD- 64 counter after 92 input pulses if the starting state is 000000?

A primary difference between a clocked J- K flip- flop and a clocked S- C flip- flop is the J- K's ability to:

Synchronous flip- flops require a clock input to change output states.

Figure 5- 1 The clocked S- C flip- flop in Figure 5- 1 is synchronized by the CLK pulse when:

As a general rule for stable flip- flop triggering, the clock pulse rise and fall times must be:

The asynchronous transfer of data between J- K storage registers can easily be accomplished using the:

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

Select the statement that best describes the two possible output states of a flip- flop.

The preset and clear inputs to a J- K flip- flop are HIGH (1). Which of the following is TRUE?

The usual stable state for one- shot is: Q = 1, Q = 0.

What type of multivibrator produces a continuous pulse train?

The three libraries in Altara's Quartus II development system software are named_____ ,_____ and_____ .

Which of the following statements best describes an asynchronous digital system?

A flip- flop is always SET by the positive- going transition that occurs when power is first applied.

Retriggerable one- shots tend to reduce the HIGH (quasi- stable) output time upon successive triggers.

Flip- flops are integral to all electronic data transfer and memory systems.

When operated in its_____mode, a FF changes states with each clock pulse.

A 1.5 MHZ clock signal is applied to an eight flip- flop binary counter. Which of the following indicates the proper MOD number, maximum number of counts, maximum count, and output frequency of the circuit?

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

The three libraries in Altara's Quartus II development system software are named___ ,_ and___ .