Question 1

An astable multivibrator:

Accepted Answer

A)  is a free running multivibrator. 
B)  uses RC circuits to determine operating frequency. 
C)  has no stable state. 
D)  All of the above 
A)  is a free running multivibrator. 
B)  uses RC circuits to determine operating frequency. 
C)  has no stable state. 
D)  All of the above

Question 2

A_____input to a S- R flip- flop results in an output state of Q = 1, Q = 0.

Accepted Answer

The answer of A_____input to a S- R flip- flop...

Question 3

A clock transition from a LOW (0) to a HIGH (1) is called a _____ transition.

Accepted Answer

The answer of A clock transition from a LOW (0)...

Question 4

An internal_______________is primarily responsible for certain flip- flops to be designated as edge- triggered.

Accepted Answer

A)  Edge- detection circuit 
B)  Pulse- steering circuit 
C)  NOR latch 
D)  NAND latch 
A)  Edge- detection circuit 
B)  Pulse- steering circuit 
C)  NOR latch 
D)  NAND latch

Question 5

A NAND latch has outputs of Q = 1 and   = 0. What effect will applying a LOW to the CLEAR input have on the latch?

Accepted Answer

A)  Q will go LOW and  will go HIGH. 
B)  It will have no effect because a HIGH input is required to change NAND latch states. 
C)  Q will remain HIGH and   will remain LOW. 
D)  It will have no effect because the latch is already in the CLEAR state. 
A)  Q will go LOW and  will go HIGH. 
B)  It will have no effect because a HIGH input is required to change NAND latch states. 
C)  Q will remain HIGH and   will remain LOW. 
D)  It will have no effect because the latch is already in the CLEAR state.

Question 6

What factors determine the duration of the quasi- stable output pulse from a one- shot multivibrator?

Accepted Answer

A)  An external resistor and capacitor 
B)  An external Schmitt- trigger circuit 
C)  The time between input trigger pulses 
D)  The duration of the input trigger pulse 
A)  An external resistor and capacitor 
B)  An external Schmitt- trigger circuit 
C)  The time between input trigger pulses 
D)  The duration of the input trigger pulse

Question 7

A D- type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

Accepted Answer

A) True 
 B)False

Question 8

Asynchronous flip- flop preset and clear inputs generally:

Accepted Answer

A)  cause the outputs to change states depending on the SR, JK, or similar controlling inputs. 
B)  clear the inputs so the flip- flop can start over. 
C)  cause the outputs to change states as soon as the input clock makes the desired transition. 
D)  act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions. 
A)  cause the outputs to change states depending on the SR, JK, or similar controlling inputs. 
B)  clear the inputs so the flip- flop can start over. 
C)  cause the outputs to change states as soon as the input clock makes the desired transition. 
D)  act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions.

Question 9

The setup time (ts) of a flip- flop indicates the length of time a control input signal must be maintained at the proper level during active CLK transition time.

Accepted Answer

A) True 
 B)False

Question 10

A flip- flop is a discrete electronic component.

Accepted Answer

A) True 
 B)False

Question 11

The setup time of a clocked flip- flop is:

Accepted Answer

A)  the minimum amount of time that an input must remain stable before an active clock transition. 
B)  the maximum amount of time that an output must remain stable after an active clock transition. 
C)  the minimum amount of time that an input must remain stable after an active clock transition. 
D)  the minimum amount of time that an output must remain stable before an active clock transition. 
A)  the minimum amount of time that an input must remain stable before an active clock transition. 
B)  the maximum amount of time that an output must remain stable after an active clock transition. 
C)  the minimum amount of time that an input must remain stable after an active clock transition. 
D)  the minimum amount of time that an output must remain stable before an active clock transition.

Question 12

All flip- flops hold the last logic level entered indefinitely.

Accepted Answer

A) True 
 B)False

Question 13

A(n) _____	input requires a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

Accepted Answer

The answer of A(n) _____	input requires a clock (CLK) or...

Question 14

In HI- Z mode, data from the bus cannot be loaded to or retrieved from a D flip- flop.

Accepted Answer

A) True 
 B)False

Question 15

Parallel data transfers between two different sets of registers requires more than one shift pulse.

Accepted Answer

A) True 
 B)False

Question 16

Due to very low current consumption by digital IC inputs, a pull- up resistor can provide a logic high with an open switch.

Accepted Answer

A) True 
 B)False

Question 17

The MOD number of a counter:

Accepted Answer

A)  indicates the number of possible counter output states. 
B)  indicates the value of the highest state. 
C)  indicates the value of the lowest state. 
D)  indicates sum of inputs. 
A)  indicates the number of possible counter output states. 
B)  indicates the value of the highest state. 
C)  indicates the value of the lowest state. 
D)  indicates sum of inputs.

Question 18

The ABEL statement Q = (D & EN) !QBAR means that the output Q will be:

Accepted Answer

A)  HIGH if D and EN variables are HIGH, or if   is LOW. 
B)  LOW if D and EN variables are HIGH and   is LOW. 
C)  HIGH if D and EN variables are HIGH and   is LOW. 
D)  LOW if D and EN variables are HIGH, or if   is LOW. 
A)  HIGH if D and EN variables are HIGH, or if   is LOW. 
B)  LOW if D and EN variables are HIGH and   is LOW. 
C)  HIGH if D and EN variables are HIGH and   is LOW. 
D)  LOW if D and EN variables are HIGH, or if   is LOW.

Question 19

Determine the output frequency for a binary counter that contains twelve flip- flops with an input clock frequency of 20.48 MHz.

Accepted Answer

A)  30.24 kHz 
B)  5 kHz 
C)  15 kHz 
D)  10.24 kHz 
A)  30.24 kHz 
B)  5 kHz 
C)  15 kHz 
D)  10.24 kHz

Question 20

A flip- flop is also referred to as a_____multivibrator.

Accepted Answer

The answer of A flip- flop is also referred to...

An astable multivibrator:

A_____input to a S- R flip- flop results in an output state of Q = 1, Q = 0.

A clock transition from a LOW (0) to a HIGH (1) is called a _____ transition.

An internal_______________is primarily responsible for certain flip- flops to be designated as edge- triggered.

A NAND latch has outputs of Q = 1 and = 0. What effect will applying a LOW to the CLEAR input have on the latch?

What factors determine the duration of the quasi- stable output pulse from a one- shot multivibrator?

A D- type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

Asynchronous flip- flop preset and clear inputs generally:

The setup time (t_s) of a flip- flop indicates the length of time a control input signal must be maintained at the proper level during active CLK transition time.

A flip- flop is a discrete electronic component.

The setup time of a clocked flip- flop is:

All flip- flops hold the last logic level entered indefinitely.

A(n) _____ input requires a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

In HI- Z mode, data from the bus cannot be loaded to or retrieved from a D flip- flop.

Parallel data transfers between two different sets of registers requires more than one shift pulse.

Due to very low current consumption by digital IC inputs, a pull- up resistor can provide a logic high with an open switch.

The MOD number of a counter:

The ABEL statement Q = (D & EN) !QBAR means that the output Q will be:

Determine the output frequency for a binary counter that contains twelve flip- flops with an input clock frequency of 20.48 MHz.

A flip- flop is also referred to as a_____multivibrator.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 5: Flip-Flops and Related Devices

An astable multivibrator:

A_____input to a S- R flip- flop results in an output state of Q = 1, Q = 0.

A clock transition from a LOW (0) to a HIGH (1) is called a _____ transition.

An internal_______________is primarily responsible for certain flip- flops to be designated as edge- triggered.

A NAND latch has outputs of Q = 1 and = 0. What effect will applying a LOW to the CLEAR input have on the latch?

What factors determine the duration of the quasi- stable output pulse from a one- shot multivibrator?

A D- type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

Asynchronous flip- flop preset and clear inputs generally:

The setup time (ts) of a flip- flop indicates the length of time a control input signal must be maintained at the proper level during active CLK transition time.

A flip- flop is a discrete electronic component.

The setup time of a clocked flip- flop is:

All flip- flops hold the last logic level entered indefinitely.

A(n) _____ input requires a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

In HI- Z mode, data from the bus cannot be loaded to or retrieved from a D flip- flop.

Parallel data transfers between two different sets of registers requires more than one shift pulse.

Due to very low current consumption by digital IC inputs, a pull- up resistor can provide a logic high with an open switch.

The MOD number of a counter:

The ABEL statement Q = (D & EN) !QBAR means that the output Q will be:

Determine the output frequency for a binary counter that contains twelve flip- flops with an input clock frequency of 20.48 MHz.

A flip- flop is also referred to as a_____multivibrator.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

The setup time (t_s) of a flip- flop indicates the length of time a control input signal must be maintained at the proper level during active CLK transition time.