Question 1

‪  
-The 'X' in the CLK/X input in Figure 9- 10 is normally called the _______	, and, in this example, is an active _______level.

Accepted Answer

A)  ENABLE, HIGH 
B)  STROBE, LOW 
C)  STROBE, HIGH 
D)  NOT CLOCK, LOW 
A)  ENABLE, HIGH 
B)  STROBE, LOW 
C)  STROBE, HIGH 
D)  NOT CLOCK, LOW

Question 2

In order to check the CLR function of a counter, which action should be taken?

Accepted Answer

A)  Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state. 
B)  Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling. 
C)  Ground the CLR input and check to be sure that all of the Q outputs are LOW. 
D)  Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH. 
A)  Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state. 
B)  Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling. 
C)  Ground the CLR input and check to be sure that all of the Q outputs are LOW. 
D)  Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH.

Question 3

‪  
-What function does the counter shown in Figure 9- 5 perform during period A on the timing diagram?

Accepted Answer

A)  Loading 
B)  Counting down 
C)  Counting up 
D)  Inhibited 
A)  Loading 
B)  Counting down 
C)  Counting up 
D)  Inhibited

Question 4

The register output expression Q0 = D0 indicates that the output Q0 will assume the value of the D0 input on the clock pulse.

Accepted Answer

A) True 
 B)False

Question 5

Which of the following procedures would be used to check the parallel loading feature on a counter?

Accepted Answer

A)  Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW. 
B)  Apply HIGHs to all the Q terminals, pulse the CLK and check to see if the DATA terminals now match the Q outputs. 
C)  Preset the LOAD inputs, set the CLR to its active level and check to see that the Q outputs match the values preset into the LOAD inputs. 
D)  Apply LOWs to the parallel DATA inputs, pulse the CLK input and check for LOWs on all the Q outputs. 
A)  Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW. 
B)  Apply HIGHs to all the Q terminals, pulse the CLK and check to see if the DATA terminals now match the Q outputs. 
C)  Preset the LOAD inputs, set the CLR to its active level and check to see that the Q outputs match the values preset into the LOAD inputs. 
D)  Apply LOWs to the parallel DATA inputs, pulse the CLK input and check for LOWs on all the Q outputs.

Question 6

‪  
-The purpose of the connection between 'C' of the 'CTR DIV 10' circuit and the 'EN' of the 'BCD/DEC' circuit in Figure 9- 10 is to _______	and is referred to as _______	.

Accepted Answer

A)  reduce the number of inputs, enabling 
B)  speed up the counter, strobing 
C)  clock the counter, strobing 
D)  eliminate glitches, strobing 
A)  reduce the number of inputs, enabling 
B)  speed up the counter, strobing 
C)  clock the counter, strobing 
D)  eliminate glitches, strobing

Question 7

Basic counters can be cascaded to increase the number of count states the counter can produce.

Accepted Answer

A) True 
 B)False

Question 8

What decimal value is required to produce an output at 'X' in this circuit?

Accepted Answer

A)  1 
B)  2 
C)  5 
D)  1 or 4 
A)  1 
B)  2 
C)  5 
D)  1 or 4

Question 9

Another term used to describe up/down counters is bidirectional.

Accepted Answer

A) True 
 B)False

Question 10

‪  
-What is the output frequency of the counter in Figure 9- 9?

Accepted Answer

A)  210.5 kHz 
B)  800 Hz 
C)  4 MHz 
D)  20 kHz 
A)  210.5 kHz 
B)  800 Hz 
C)  4 MHz 
D)  20 kHz

Question 11

‪  
-The circuit in Figure 9- 2 is a(n)__________ 	.

Accepted Answer

A)  two- bit asynchronous binary counter 
B)  eight- bit asynchronous binary flip- flop 
C)  four- bit asynchronous binary counter 
D)  three- bit synchronous binary counter 
A)  two- bit asynchronous binary counter 
B)  eight- bit asynchronous binary flip- flop 
C)  four- bit asynchronous binary counter 
D)  three- bit synchronous binary counter

Question 12

Once an up/down counter begins its count sequence, it cannot be reversed.

Accepted Answer

A) True 
 B)False

Question 13

‪  
-The counter in Figure 9- 5 is counting DOWN; when the count reaches zero, the MAX/MIN output will go ________.

Accepted Answer

A)  HIGH 
B)  LOW 
A)  HIGH 
B)  LOW

Question 14

The term synchronous refers to events that do not occur at the same time.

Accepted Answer

A) True 
 B)False

Question 15

‪  
-What is the meaning of the label 'CTR DIV 16' on the 74LS163A diagram shown in Figure 9- 4?

Accepted Answer

A)  The circuit is a four- bit, 16- state counter. 
B)  The circuit is a control device with 16 outputs. 
C)  The circuit is a hexadecimal converter. 
D)  The circuit is a 16- bit, four- state counter. 
A)  The circuit is a four- bit, 16- state counter. 
B)  The circuit is a control device with 16 outputs. 
C)  The circuit is a hexadecimal converter. 
D)  The circuit is a 16- bit, four- state counter.

Question 16

Asynchronous counters are often called __________counters.

Accepted Answer

A)  binary 
B)  flip- flop 
C)  ripple 
D)  toggle 
A)  binary 
B)  flip- flop 
C)  ripple 
D)  toggle

Question 17

Modulus refers to_________.

Accepted Answer

A)  the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another 
B)  an input on a counter that is used to set the counter state, such as UP/DOWN 
C)  a method used to fabricate decade counter units 
D)  the maximum number of states in a counter sequence 
A)  the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another 
B)  an input on a counter that is used to set the counter state, such as UP/DOWN 
C)  a method used to fabricate decade counter units 
D)  the maximum number of states in a counter sequence

Question 18

‪  
-The circuit shown in Figure 9- 3 represents a(n) __________	.

Accepted Answer

A)  asynchronous BCD decade counter 
B)  synchronous BCD decade counter 
C)  BCD- to- decimal decoder 
D)  four- bit binary counter 
A)  asynchronous BCD decade counter 
B)  synchronous BCD decade counter 
C)  BCD- to- decimal decoder 
D)  four- bit binary counter

Question 19

A decade counter counts from zero (0) through decimal __________.

Accepted Answer

A)  9 
B)  15 
C)  0 
D)  10 
A)  9 
B)  15 
C)  0 
D)  10

Question 20

Which of the following statements best describes the operation of an UP/DOWN SYNCHRONOUS COUNTER?

Accepted Answer

A)  The counter can count in either direction, but must continue in that direction once started. 
B)  In general, the counter can be reversed at any point in its counting sequence. 
C)  The counter can be reversed, but must be RESET before counting in the other direction. 
D)  The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero. 
A)  The counter can count in either direction, but must continue in that direction once started. 
B)  In general, the counter can be reversed at any point in its counting sequence. 
C)  The counter can be reversed, but must be RESET before counting in the other direction. 
D)  The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero.

‪ -The 'X' in the CLK/X input in Figure 9- 10 is normally called the _ , and, in this example, is an active _level.

In order to check the CLR function of a counter, which action should be taken?

‪ -What function does the counter shown in Figure 9- 5 perform during period A on the timing diagram?

The register output expression Q₀= D₀indicates that the output Q₀will assume the value of the D₀input on the clock pulse.

Which of the following procedures would be used to check the parallel loading feature on a counter?

‪ -The purpose of the connection between 'C' of the 'CTR DIV 10' circuit and the 'EN' of the 'BCD/DEC' circuit in Figure 9- 10 is to _ and is referred to as _ .

Basic counters can be cascaded to increase the number of count states the counter can produce.

What decimal value is required to produce an output at 'X' in this circuit?

Another term used to describe up/down counters is bidirectional.

‪ -What is the output frequency of the counter in Figure 9- 9?

‪ -The circuit in Figure 9- 2 is a(n)__________ .

Once an up/down counter begins its count sequence, it cannot be reversed.

‪ -The counter in Figure 9- 5 is counting DOWN; when the count reaches zero, the MAX/MIN output will go ________.

The term synchronous refers to events that do not occur at the same time.

‪ -What is the meaning of the label 'CTR DIV 16' on the 74LS163A diagram shown in Figure 9- 4?

Asynchronous counters are often called __________counters.

Modulus refers to_________.

‪ -The circuit shown in Figure 9- 3 represents a(n) __________ .

A decade counter counts from zero (0) through decimal __________.

Which of the following statements best describes the operation of an UP/DOWN SYNCHRONOUS COUNTER?

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Latches, Flip-Flops, and Timers

Shift Registers

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters

Exam 9: Counters

‪ -The 'X' in the CLK/X input in Figure 9- 10 is normally called the _______ , and, in this example, is an active _______level.

In order to check the CLR function of a counter, which action should be taken?

‪ -What function does the counter shown in Figure 9- 5 perform during period A on the timing diagram?

The register output expression Q0 = D0 indicates that the output Q0 will assume the value of the D0 input on the clock pulse.

Which of the following procedures would be used to check the parallel loading feature on a counter?

‪ -The purpose of the connection between 'C' of the 'CTR DIV 10' circuit and the 'EN' of the 'BCD/DEC' circuit in Figure 9- 10 is to _______ and is referred to as _______ .

Basic counters can be cascaded to increase the number of count states the counter can produce.

What decimal value is required to produce an output at 'X' in this circuit?

Another term used to describe up/down counters is bidirectional.

‪ -What is the output frequency of the counter in Figure 9- 9?

‪ -The circuit in Figure 9- 2 is a(n)__________ .

Once an up/down counter begins its count sequence, it cannot be reversed.

‪ -The counter in Figure 9- 5 is counting DOWN; when the count reaches zero, the MAX/MIN output will go ________.

The term synchronous refers to events that do not occur at the same time.

‪ -What is the meaning of the label 'CTR DIV 16' on the 74LS163A diagram shown in Figure 9- 4?

Asynchronous counters are often called __________counters.

Modulus refers to_________.

‪ -The circuit shown in Figure 9- 3 represents a(n) __________ .

A decade counter counts from zero (0) through decimal __________.

Which of the following statements best describes the operation of an UP/DOWN SYNCHRONOUS COUNTER?

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Latches, Flip-Flops, and Timers

Shift Registers

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters

‪ -The 'X' in the CLK/X input in Figure 9- 10 is normally called the _ , and, in this example, is an active _level.

The register output expression Q₀= D₀indicates that the output Q₀will assume the value of the D₀input on the clock pulse.

‪ -The purpose of the connection between 'C' of the 'CTR DIV 10' circuit and the 'EN' of the 'BCD/DEC' circuit in Figure 9- 10 is to _ and is referred to as _ .