Question 1

A one- shot is classified as a(n) _________.

Accepted Answer

A)  one- pulse multivibrator 
B)  bistable multivibrator 
C)  astable multivibrator 
D)  monostable multivibrator 
A)  one- pulse multivibrator 
B)  bistable multivibrator 
C)  astable multivibrator 
D)  monostable multivibrator

Question 2

A pulse- triggered flip- flop is identified by a bubble on its Q output terminal.

Accepted Answer

A) True 
 B)False

Question 3

If both inputs of an S- R flip- flop are low, what happens when the clock goes high?

Accepted Answer

A)  The output toggles. 
B)  An invalid state is produced. 
C)  The output resets. 
D)  No change occurs in the output. 
A)  The output toggles. 
B)  An invalid state is produced. 
C)  The output resets. 
D)  No change occurs in the output.

Question 4

The waveforms for this J- K flip- flop indicate the circuit is operating properly.

Accepted Answer

A) True 
 B)False

Question 5

Flip- flops are normally used for all of the following applications, except _________.

Accepted Answer

A)  logic gates 
B)  frequency division 
C)  data storage 
D)  counting 
A)  logic gates 
B)  frequency division 
C)  data storage 
D)  counting

Question 6

What advantage does a J- K flip- flop have over an R- S flip- flop?

Accepted Answer

A)  It does not require a clock input. 
B)  It has only one output. 
C)  It has no invalid input states. 
D)  It has fewer gates. 
A)  It does not require a clock input. 
B)  It has only one output. 
C)  It has no invalid input states. 
D)  It has fewer gates.

Question 7

Pulse- triggered flip- flops are also called_______flip- flops.

Accepted Answer

A)  postponed 
B)  master- slave 
C)  edge 
D)  level 
A)  postponed 
B)  master- slave 
C)  edge 
D)  level

Question 8

Which of the following is a primary characteristic of the data lock- out flip- flop?

Accepted Answer

A)  Data can only be entered when the clock is high. 
B)  Data is only clocked into the FF on the clock transition. 
C)  Data cannot be entered into the FF unless the EN line is high. 
D)  The master section is a pulse triggered type FF. 
A)  Data can only be entered when the clock is high. 
B)  Data is only clocked into the FF on the clock transition. 
C)  Data cannot be entered into the FF unless the EN line is high. 
D)  The master section is a pulse triggered type FF.

Question 9

Which of the following ratings is not associated with flip- flops?

Accepted Answer

A)  Set- up time 
B)  Propagation delay time 
C)  Hold time 
D)  Interval time 
A)  Set- up time 
B)  Propagation delay time 
C)  Hold time 
D)  Interval time

Question 10

An edge- triggered flip- flop must have ______.

Accepted Answer

A)  at least two inputs to handle rising and falling edges 
B)  a pulse transition detector 
C)  a very fast response time 
D)  active- low inputs and complemented outputs 
A)  at least two inputs to handle rising and falling edges 
B)  a pulse transition detector 
C)  a very fast response time 
D)  active- low inputs and complemented outputs

Question 11

Preset and Clear inputs are normally synchronous.

Accepted Answer

A) True 
 B)False

Question 12

A retriggerable one- shot has a pulse width of 10 ms. Three milliseconds (3 ms) after being triggered, another trigger pulse is applied. The duration of the resulting output pulse will be_________ms

Accepted Answer

A)  10 
B)  3 
C)  7 
D)  13 
A)  10 
B)  3 
C)  7 
D)  13

Question 13

The 555 timer has three basic operating modes: monostable, bistable, and astable.

Accepted Answer

A) True 
 B)False

Question 14

A D flip- flop is constructed by connecting an inverter between the Set and Clock terminals of a S- R flip- flop.

Accepted Answer

A) True 
 B)False

Question 15

Asynchronous inputs are best described as________.

Accepted Answer

A)  having little or no control over the FF, except during the active clock input 
B)  being tied to the clock, but not to the inputs 
C)  being tied to the inputs, but independent of the clock 
D)  having full control over the FF, regardless of the input or clock states 
A)  having little or no control over the FF, except during the active clock input 
B)  being tied to the clock, but not to the inputs 
C)  being tied to the inputs, but independent of the clock 
D)  having full control over the FF, regardless of the input or clock states

Question 16

A J- K flip- flop can be used as a divide- by- two frequency divider with an output duty cycle of 50%.

Accepted Answer

A) True 
 B)False

Question 17

Which of the following best describes the action of pulse- triggered flip- flops?

Accepted Answer

A)  A pulse on the clock transfers data from input to output. 
B)  The synchronous inputs must be pulsed. 
C)  The clock and R- S inputs must be pulse shaped. 
D)  The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. 
A)  A pulse on the clock transfers data from input to output. 
B)  The synchronous inputs must be pulsed. 
C)  The clock and R- S inputs must be pulse shaped. 
D)  The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.

Question 18

Set- up time specifies ________ .

Accepted Answer

A)  how long it takes the output to change states after the clock has transitioned 
B)  the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF 
C)  the minimum time required for the control levels to be maintained at the inputs of a flip- flop prior to the triggering edge of the clock in order for data to be reliably clocked into the component 
D)  how long the operator has in order to get the flip- flop running before the maximum power level is exceeded 
A)  how long it takes the output to change states after the clock has transitioned 
B)  the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF 
C)  the minimum time required for the control levels to be maintained at the inputs of a flip- flop prior to the triggering edge of the clock in order for data to be reliably clocked into the component 
D)  how long the operator has in order to get the flip- flop running before the maximum power level is exceeded

A one- shot is classified as a(n) _________.

A pulse- triggered flip- flop is identified by a bubble on its Q output terminal.

If both inputs of an S- R flip- flop are low, what happens when the clock goes high?

The waveforms for this J- K flip- flop indicate the circuit is operating properly.

Flip- flops are normally used for all of the following applications, except _________.

What advantage does a J- K flip- flop have over an R- S flip- flop?

Pulse- triggered flip- flops are also called_______flip- flops.

Which of the following is a primary characteristic of the data lock- out flip- flop?

Which of the following ratings is not associated with flip- flops?

An edge- triggered flip- flop must have ______.

Preset and Clear inputs are normally synchronous.

A retriggerable one- shot has a pulse width of 10 ms. Three milliseconds (3 ms) after being triggered, another trigger pulse is applied. The duration of the resulting output pulse will be_________ms

The 555 timer has three basic operating modes: monostable, bistable, and astable.

A D flip- flop is constructed by connecting an inverter between the Set and Clock terminals of a S- R flip- flop.

Asynchronous inputs are best described as________.

A J- K flip- flop can be used as a divide- by- two frequency divider with an output duty cycle of 50%.

Which of the following best describes the action of pulse- triggered flip- flops?

Set- up time specifies ________ .

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Shift Registers

Counters

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters

Exam 7: Latches, Flip-Flops, and Timers

A one- shot is classified as a(n) _________.

A pulse- triggered flip- flop is identified by a bubble on its Q output terminal.

If both inputs of an S- R flip- flop are low, what happens when the clock goes high?

The waveforms for this J- K flip- flop indicate the circuit is operating properly.

Flip- flops are normally used for all of the following applications, except _________.

What advantage does a J- K flip- flop have over an R- S flip- flop?

Pulse- triggered flip- flops are also called_______flip- flops.

Which of the following is a primary characteristic of the data lock- out flip- flop?

Which of the following ratings is not associated with flip- flops?

An edge- triggered flip- flop must have ______.

Preset and Clear inputs are normally synchronous.

A retriggerable one- shot has a pulse width of 10 ms. Three milliseconds (3 ms) after being triggered, another trigger pulse is applied. The duration of the resulting output pulse will be_________ms

The 555 timer has three basic operating modes: monostable, bistable, and astable.

A D flip- flop is constructed by connecting an inverter between the Set and Clock terminals of a S- R flip- flop.

Asynchronous inputs are best described as________.

A J- K flip- flop can be used as a divide- by- two frequency divider with an output duty cycle of 50%.

Which of the following best describes the action of pulse- triggered flip- flops?

Set- up time specifies ________ .

Introductory Concepts

Number Systems, Operations, and Codes

Logic Gates

Boolean Algebra and Logic Simplification

Combinational Logic Analysis

Functions of Combinational Logic

Shift Registers

Counters

Programmable Logic

Data Storage

Signal Conversion and Processing

Data Transmission

Data Processing and Control

Integrated Circuit Technologies

Filters