Exam 20: Control Unit Operation

The _________ is connected to the address lines of the system bus.

The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.

For the control unit to perform its function it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system.

Each instruction executed during an instruction cycle is made up of shorter ______.

The execute cycle is simple and predictable.

The timing of processor operations is synchronized by the __________ and controlled by the control unit with control signals.

The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other.

The use of common data paths simplifies the interconnection layout and the control of the processor.

If the instruction specifies an indirect address,then a(n)________ cycle must precede the execute cycle.

The _________ of a processor generates the control signals that cause each micro-operation to be executed.

The _____________ must control the state of the instruction cycle.

One technique for implementing a control unit is referred to as hardwired implementation,in which the control unit is essentially a state machine circuit.

Each of the smaller cycles involves a series of steps,each of which involves the processor registers,referred to as _________.

Which of the following is an Intel 8085 external signal?

The _________ cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory.

The __________ register specifies the address in memory for a read or write operation.

The _______ designates the state of the processor in terms of which portion of the cycle it is in.

The groupings of micro-operations must follow which rule?

The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program.

At the completion of the execute cycle a test is made to determine whether any enabled interrupts have occurred,and if they have,the interrupt cycle occurs.