Exam 14: Processor Structure and Function

Many processor designs include a register or set of registers often known as the _________ that contain status information and condition codes.

__________ or fetch overlap is where,while the second stage is executing the instruction,the first stage takes advantage of any unused memory cycles to fetch and buffer the next instruction.

The OS usually runs in ________.

A ________ hazard occurs when there is a conflict in the access of an operand location.

Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.

While the processor is in user mode the program being executed is unable to access protected system resources or to change mode,other than by causing an exception to occur.

Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.

The _________ contains the address of an instruction to be fetched.

It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

__________ is a process where new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.

A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.

A _________,also known as a branch hazard,occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.

A processor must: fetch instruction,interpret instruction,process data,write data,and _________.

The ________ controls the movement of data and instructions into and out of the processor.

The _________ stage includes ALU operations,cache access,and register update.

An instruction cycle includes the following stages: fetch,execute,and _______.

Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.