Exam 18: Multicore Computers

The Intel Core i7-990X chip supports _________ forms of external communications to other chips.

Even if an individual application does not scale to take advantage of a large number of threads,it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.

With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.

Direct data intervention enables copying clean data from one CPU L1 data cache to another CPU L1 data cache without accessing external memory.

The ________ is responsible for maintaining coherency among L1 data caches.

An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.

A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.

The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.

The generic timer handles interrupt detection and interrupt prioritization.

A single piece of silicon is called a ________.

_______ applications embrace threading in a fundamental way.

The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.

_________ is when multiple pipelines are constructed by replicating execution resources,enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided.

The principal building block of the IBM zEnterprise EC12 mainframe is the __________ .

_______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.

From the point of view of an A15 core,an interrupt can be active,inactive,or __________ .

The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.

Individual modules called systems are assigned to individual processors with ________ threading.

The GIC distributes interrupts to individual _________.

With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread.