Exam 15: Reduced Instruction Set Computers

The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.

When using graph coloring,nodes that share the same color cannot be assigned to the same register.

Although a variety of different approaches to reduced instruction set architecture have been taken,certain characteristics are common to all of them: register-to-register operations,simple addressing modes,simple instruction formats,and __________.

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.

The acronym CISC stands for _________.

Individual variables,compiler assigned global variables,register addressing,and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.

A tactic similar to the delayed branch is the _________,which can be used on LOAD instructions.

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses,registers,and the ALU.

The acronym SPARC stands for __________.

Which stage is required for load and store operations?

The register file is on the same chip as the ALU and control unit.

The major cost in the life cycle of a system is hardware.

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.

The instruction location immediately following the delayed branch is referred to as the ________.

The acronym RISC stands for __________.

With simple,one cycle instructions,there is little or no need for microcode.

The cache is capable of handling global as well as local variables.

Almost all RISC instructions use simple register addressing.