Exam 17: Parallel Processing

An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol.

Software cache coherence schemes attempt to avoid the need for additional hardware circuitry and logic by relying on the compiler and operating system to deal with the problem.

The objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system.

A taxonomy first introduced by _______ is still the most common way of categorizing systems with parallel processing capability.

Computer systems that fall into the ________ category have a set of processors that simultaneously execute different instruction sequences on different data sets.

________ provides service to customers in the form of software,specifically application software,running on and accessible in the cloud.

The four principal approaches to multithreading are: interleaved (fine-grained),blocked (coarse-grained),simultaneous,and ________.

The function of switching applications and data resources over from a failed system to an alternative system in the cluster is referred to as failback.

The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture.

A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously,and if processors are allowed to update their own copies freely,an inconsistent view of memory can result.

Computer systems that fall into the __________ category have a single processor that executes a single instruction stream to operate on data stored in a single memory.

With no multithreading,_________ is the simple pipeline found in traditional RISC and CISC machines.

Vector and array processors fall into the ________ category of computer systems.

SMPs,clusters,and NUMA systems fit into the ________ category of computer systems.

A ________ is a dispatchable unit of work within a process that includes a processor context and its own data area for a stack.

Snoopy protocols are not suitable for a bus-based multiprocessor.

The most important measure of performance for a processor is the rate at which it executes instructions.

Hardware-based solutions are generally referred to as cache coherence _______.

With a write-update protocol there can be multiple readers but only one writer at a time.

Replicating the entire processor on a single chip with each processor handling separate threads is _________.