Exam 3: A Top-Level View of Computer Function and Interconnection

A key characteristic of a bus is that it is not a shared transmission medium.

The basic function of a computer is to execute programs.

The von Neumann architecture is based on which concept?

The _________ lines are used to control the access to and the use of the data and address lines.

With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.

The collection of paths connecting the various modules is called the _________ structure.

With asynchronous timing the occurrence of events on the bus is determined by a clock.

A __________ is the high-level set of rules for exchanging packets of data between devices.

The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.

A bus that connects major computer components (processor,memory,I / O)is called a __________.

A(n)_________ is generated by a failure such as power failure or memory parity error.

Interrupts do not improve processing efficiency.

A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.

A(n)________ interrupt is generated by an I / O controller to signal normal completion of an operation,request service from the processor,or to signal a variety of error conditions.

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

The processing required for a single instruction is called a(n)__________ cycle.

A __________ register specifies the address in memory for the next read or write.

A __________ is a communication pathway connecting two or more devices.

The __________ is a popular high-bandwidth,processor-independent bus that can function as a mezzanine or peripheral bus.

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.