Exam 18: Multicore Computers

The SCU uses hybrid MESI and _________ protocols to maintain coherency between the individual L1 data caches and the L2 cache.

The demand on power requirements has not grown as chip density and clock frequency have risen.

The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.

_______ is an animation engine used by Valve for its games and licensed for other game developers.

The _________ is a cache-coherent,point-to-point link based electrical interconnect specification for Intel processors and chipsets that enable high-speed communications among connected processor chips.

________ threading involves the selective use of fine-grain threading for some systems and single threading for other systems.

_________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline,another instruction is executing in another stage of the pipeline.

Database management systems and database applications are one area in which multicore systems can be used effectively.

__________ applications are characterized by the presence of many single-threaded processes.

_________ applications are characterized by the presence of many single-threaded processes.

The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.

One way to control power density is to use more of the chip area for ________.

__________ applications are characterized by having a small number of highly threaded processes.

With _______,register banks are replicated so that multiple threads can share the use of pipeline resources.

Putting rendering on one processor,AI on another,and physics on another is an example of _________ threading.

A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading.

________ is a multithreaded process that provides scheduling and memory management for Java applications.

_________ states that performance increase is roughly proportional to square root of increase in complexity.

The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.

__________ are characterized by the ability to support thousands of parallel execution threads