Exam 15: Reduced Instruction Set Computers

The first commercial RISC product was _________.

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

All MIPS R series processor instructions are encoded in a single ________ word format.

A ________ architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.

_________ determines the control and pipeline organization.

_________ is the fastest available storage device.

Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.

_________ instructions are used to position quantities in registers temporarily for computational operations.

A ________ is defined to be the time it takes to fetch two operands from registers,perform an ALU operation,and store the result in a register.

Procedure calls and returns are not important aspects of HLL programs.

The Patterson study examined the dynamic behavior of _________ programs,independent of the underlying architecture.

__________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.

A _________ architecture is one that makes use of more,and more fine-grained pipeline stages.

The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.

The R4000 can have as many as _______ instructions in the pipeline at the same time.

It is common for programs,both system and application,to continue to exhibit new bugs after years of operation.

The register file employs much shorter addresses than addresses for cache and memory.

The difference between the operations provided in high-level languages (HLLs)and those provided in computer architecture is known as the ________.

A ________ instruction can be used to account for data and branch delays.

A large number of general-purpose registers,and / or the use of compiler technology to optimize register usage,a limited and simple instruction set,and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.