Exam 14: Processor Structure and Function

The control unit (CU)does the actual computation or processing of data.

The ARM architecture supports _______ execution modes.

__________ are a set of storage locations.

__________ are bits set by the processor hardware as the result of operations.

The _________ contains a word of data to be written to memory or the word most recently read.

Data are exchanged with the processor from external memory through a _________.

The ________ flag allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.

The three types of data hazards are: read after write (RAW),write after write (WAW),and _________.

__________ registers are used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs.

________ is used for debugging.

The exception modes have full access to system resources and can change modes freely.

A __________ occurs when the pipeline,or some portion of the pipeline,must stall because conditions do not permit continued execution.

An interrupt is generated from software and it is provoked by the execution of an instruction.

The allocation of control information between registers and memory are not considered to be a key design issue.

The major components of the processor are an arithmetic and logic unit (ALU)and a __________.

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address.

_________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.

A _________ is a small,very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

The predict-never-taken approach is the most popular of all the branch prediction methods.

One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.