Question 1

The QPI link layer performs two key functions: flow control and _________ control.

Accepted Answer

The answer of The QPI link layer performs two key...

Question 2

The __________ are used to designate the source or destination of the data on the data bus.

Accepted Answer

A) system lines 
B) data lines 
C) control lines 
D) address lines 
A) system lines 
B) data lines 
C) control lines 
D) address lines

Question 3

A(n)_________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

Accepted Answer

The answer of A(n)_________ interrupt is generated by a timer...

Question 4

Program execution consists of repeating the process of instruction fetch and instruction execution.

Accepted Answer

A) True 
 B)False

Question 5

Timing refers to the way in which events are coordinated on the bus.

Accepted Answer

A) True 
 B)False

Question 6

The purpose of the PCIe __________ layer is to ensure reliable delivery of packets across the PCIe link.

Accepted Answer

The answer of The purpose of the PCIe __________ layer...

Question 7

The interconnection structure must support which transfer?

Accepted Answer

A) memory to processor 
B) processor to memory 
C) I / O to or from memory 
D) all of the above 
A) memory to processor 
B) processor to memory 
C) I / O to or from memory 
D) all of the above

Question 8

Each data path consists of a pair of wires (referred to as a __________ )that transmits data one bit at a time.

Accepted Answer

A) lane 
B) path 
C) line 
D) bus 
A) lane 
B) path 
C) line 
D) bus

Question 9

A sequence of codes or instructions is called __________.

Accepted Answer

A) software 
B) memory 
C) an interconnect 
D) a register 
A) software 
B) memory 
C) an interconnect 
D) a register

Question 10

The method of using the same lines for multiple purposes is known as time multiplexing.

Accepted Answer

A) True 
 B)False

Question 11

The most common classes of interrupts are: program,timer,I / O and ________.

Accepted Answer

The answer of The most common classes of interrupts are:...

Question 12

There are three important groups of DLLPs used in managing a link: flow control packets, _________________ ,and TLP ACK and NAK packets.

Accepted Answer

power mana

Question 13

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

Accepted Answer

A) transaction layer 
B) root layer 
C) configuration layer 
D) transport layer 
A) transaction layer 
B) root layer 
C) configuration layer 
D) transport layer

Question 14

The TL supports which of the following address spaces?

Accepted Answer

A) memory 
B) I / O 
C) message 
D) all of the above 
A) memory 
B) I / O 
C) message 
D) all of the above

Question 15

A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.

Accepted Answer

A) True 
 B)False

Question 16

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,Princeton.

Accepted Answer

A) John Maulchy 
B) John von Neumann 
C) Herman Hollerith 
D) John Eckert 
A) John Maulchy 
B) John von Neumann 
C) Herman Hollerith 
D) John Eckert

Question 17

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

Accepted Answer

A) True 
 B)False

Question 18

The data lines provide a path for moving data among system modules and are collectively called the _________.

Accepted Answer

A) control bus 
B) address bus 
C) data bus 
D) system bus 
A) control bus 
B) address bus 
C) data bus 
D) system bus

Question 19

A _________ register contains the data to be written into memory or receives the data read from memory.

Accepted Answer

The answer of A _________ register contains the data to...

Question 20

Because all devices on a synchronous bus are tied to a fixed clock rate,the system cannot take advantage of advances in device performance.

Accepted Answer

A) True 
 B)False

Exam 3: A Top-Level View of Computer Function and Interconnection

The QPI link layer performs two key functions: flow control and _________ control.

The __________ are used to designate the source or destination of the data on the data bus.

A(n)_________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

Program execution consists of repeating the process of instruction fetch and instruction execution.

Timing refers to the way in which events are coordinated on the bus.

The purpose of the PCIe __________ layer is to ensure reliable delivery of packets across the PCIe link.

The interconnection structure must support which transfer?

Each data path consists of a pair of wires (referred to as a __________ )that transmits data one bit at a time.

A sequence of codes or instructions is called __________.

The method of using the same lines for multiple purposes is known as time multiplexing.

The most common classes of interrupts are: program,timer,I / O and ________.

There are three important groups of DLLPs used in managing a link: flow control packets, _________________ ,and TLP ACK and NAK packets.

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

The TL supports which of the following address spaces?

A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,Princeton.

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

The data lines provide a path for moving data among system modules and are collectively called the _________.

A _________ register contains the data to be written into memory or receives the data read from memory.

Because all devices on a synchronous bus are tied to a fixed clock rate,the system cannot take advantage of advances in device performance.

Basic Concepts and Computer Evolution

Performance Issues

Cache Memory

Internal Memory

External Memory

Input Output

Operating System Support

Number Systems

Computer Arithmetic

Digital Logic

Characteristics and Functions

Addressing Modes and Formats

Processor Structure and Function

Reduced Instruction Set Computers

Parallelism and Superscalar Processors

Parallel Processing

Multicore Computers

General-Purpose Graphic Processing Units

Control Unit Operation

Microprogrammed Control

Filters