Exam 16: Parallelism and Superscalar Processors

In effect,the Intel Core architecture implements a CISC instruction set architecture on a RISC microarchitecture.

The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.

Instruction-level parallelism is also determined by __________,which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.

Which of the following is a fundamental limitation to parallelism with which the system must cope?

________ is a protocol used to issue instructions.

The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.

In the scalar organization there are multiple functional units,each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?

The term _________ parallelism refers to the degree to which,on average,the instructions of a program can be executed in parallel.

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.

The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.

An alternative to _________ is a scoreboarding.

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

Resources include: memories,caches,buses,and register-file ports.

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones,set-top boxes,gaming consoles and automotives navigation / entertainment systems.

Utilizing a branch target buffer (BTB),the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions.

The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.

The superscalar approach depends on the ability to execute multiple instructions in parallel.

The superscalar approach can be used on __________ architecture.

The superscalar approach has now become the standard method for implementing high-performance microprocessors.