Exam 16: Parallelism and Superscalar Processors

________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.

________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.

The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.

In-order completion requires more complex instruction issue logic than out-of-order completion.

A _________ is a competition of two or more instructions for the same resource at the same time.